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Statistical Simulation of Metal-Gate Work-function Fluctuation in High-kappa/Metal-Gate Devices
(2010)
Yu, Chia-Hui
;
Han, Ming-Hung
;
Cheng, Hui-Wen
;
Su, Zhong-Cheng
;
Li, Yiming
In this work, we statistically examine the emerging high-kappa / metal gate work-function fluctuation (WKF) induced threshold voltage (V(th)) fluctuations in 16-nm-gate MOSFET devices. Our Monte-Carlo model extensively evaluates the impact of WKF for different technology node, metal grain size, and gate material. This model provides us to identify suitable materials and fabrication processes that can significantly reduce the impact of Vth fluctuation owing to WKF. First, four kinds of gate material are examined and TiN possesses the smallest Vth fluctuation. For fabrication process, a fast deposition of metal at lower temperature prevents the metal grain not to grow to large size result in a smaller variation. In addition, an idea of modeling multilayer metal gate WKF is also presented and discussed, in which the first layer plays the most important role, compared with other layers, for the fluctuation suppression.
Simulation of electrical characteristics of surrounding- and omega-shaped-gate nanowire FinFETs
(2004)
Tang, CS
;
Yu, SM
;
Chou, HM
;
Lee, JW
;
Li, YM
In this paper, electrical characteristics of sub-10 not nanowire FinFETs are investigated using a three-dimensional (3D) quantum correction simulation. Two different nanowire FinFETs, surrounding-gate FinFET and omega-shaped-gate one, are simulated with density-gradient-based model and compared in terms of on/off current, turn-on resistance, gate capacitance. It is found that the characteristic difference between surrounding-gate FinFET and omega-shaped-gate FinFET with a 70% coverage is insignificant. However, the former possesses better DIBL effect than that latter with different coverage ratios. Our examination presented here is useful in the fabrication of omega-shaped nanowire FinFETs.
A study of the threshold voltage variations for ultrathin body double gate SOI MOSFETs
(2004)
Tang, CS
;
Lo, SC
;
Lee, JW
;
Tsai, JH
;
Li, YM
Silicon on insulator (SOI) devices have been of great interest in these years. In this paper, simulation with density-gradient transport model is performed to examine the variation of threshold voltage (VTH) for double gate SOI MOSFETs. Different thickness of silicon (Si) film, oxide thickness, channel length and doping concentration are considered in this work. According to the numerical study, both drift-difftision (DD) and density gradient (DG) models demonstrate that the thickness of Si film greatly affects the threshold voltage (5 similar to 15% variation). It is found that the thickness of Si film decreases, VTH variation increases; and the dependence relation is nonlinear. Therefore, this effect must be taken into account for the realization of double gate SOI ULSI circuit.
Statistical Analysis of Metal Gate Workfunction Variability, Process Variation, and Random Dopant Fluctuation in Nano-CMOS Circuits
(2009)
Hwang, Chih-Hong
;
Li, Tien-Yeh
;
Han, Ming-Hung
;
Lee, Kuo-Fu
;
Cheng, Hui-Wen
This work for the first time estimates the influences of the intrinsic parameter fluctuations consisting of metal gate workfunction fluctuation (WKF), process variation effect (PVE) and random dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field effect transistors (MOSFETs) and circuits. The WKF and RDF dominate the threshold voltage fluctuation; however, the WKF brings less impact on the gate capacitance due to the screening effect of the inversion layer. The fluctuation of timing characteristics depends on the threshold voltage fluctuation, and therefore is proportional to the trend of threshold voltage fluctuation. For an amplifier circuit, the high-frequency characteristics, the circuit gain, the 3dB bandwidth, the unity-gain bandwidth power, and the power-added efficiency, are explored consequently. Similar to the trend of the cutoff frequency, the PVE and RDF dominate both the device and circuits characteristic fluctuations due to the significant gate capacitance fluctuations and the WKF is less important at this simulation scenario. The extensive study assesses the fluctuations on circuit performance and reliability, which can in turn be used to optimize nanoscale MOSFET and circuits.
Parameterized Display Performances Behavioral Modeling and Optimization for TFT-LCD Panel
(2009)
Huang, Hsuan-Ming
;
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
In this paper, we implement a systematical method for thin film transistor liquid-crystal display (TFT-LCD) design optimization and sensitivity analysis. Based upon a three-dimensional (3D) field solver, Simulation Program with Integrated Circuit Emphasis (SPICE), and a Design of Experiments, we construct a second-order response surface model (RSM) for the performances of an interested TFT-LCD panel. The constructed RSMs are reduced using a step-wise regression. The adequacy and accuracy using the normal residual plots and their residual of squares are verified. According to the constructed models, we then analyze the sensitivity of the performances by considering the design parameters as changing factors (i.e., the size variation, position shift and driving setting) under an assumption of Gaussian distribution. We also could apply the models to optimize the designed circuit. The designing parameters of these models are selected and optimized to fit the designing target of the examined circuit by the genetic algorithm in our unified optimization framework. This computational statistics method can predict the TFT-LCD performances and show the engineering practicability in display panel industry.
Effect of Process Variation on 15-nm-Gate Stacked Multichannel Surrounding-Gate Field Effect Transistor
(2009)
Han, Ming-Hung
;
Cheng, Hui-Wen
;
Hwang, Chih-Hong
;
Li, Yiming
;
傳播研究所
Stacked multichannel transistor architectures were proposed recently which possess very attractive electrical characteristics on low leakage current and high driving current per layout area. However, due to complex manufacturing process, the process variation effect is inevitable and whose impact is unknown. Therefore, this study investigates the impact of process variation on 15-nm-gate stacked multichannel transistors consisting of the gate length deviation, channel position variation, quadruple-shaped channel structure and elliptic gate oxide. Our preliminary result shows that the stacked multichannel devices have good immunity to the gate length deviation and channel spacing variations; however, they are sensitive to the gate coverage ratio and gate oxide thickness variations. This study provides an insight into the device characteristic variations, which may benefit the development of nanoscale stacked multichannel transistors and circuits.
Numerical simulation of static noise margin for a six-transistor static random access memory cell with 32nm fin-typed field effect transistors
(2007)
Li, Yiming
;
Hwang, Chih-Hong
;
Yu, Shao-Ming
;
電信工程研究所
;
Institute of Communications Engineering
We in this paper for the first time explore the static noise margin (SNM) of a six-transistor (6T) static random access memory (SRAM) cell with nanoscale silicon-on-insulator (SOI) fin-typed field effect transistors (FinFETs). The SNM is calculated with respect to the supply voltage, operating temperature, and cell ratio by performing a three-dimensional mixed-mode simulation. To include the quantum mechanical effect, the density-gradient equation is simultaneously solved in the coupled device and circuit equations. The standard deviation (sigma-(S N M)) of SNM versus device's channel length is computed, based upon the design of experiment and response surface methodology. Compared with the result of SNM for SRAM with 32nm planar metal-oxide-semiconductor field effect transistors, SRAM with SOI FinFETs quantitatively exhibits higher SNM and lower sigma-(S N M). Improvement of characteristics resulting from good channel controllability implies that SRAM cells fabricated with FinFETs continuously maintains cell stability in sub-32nm technology nodes.
Comprehensive Examination of Threshold Voltage Fluctuations in Nanoscale Planar MOSFET and Bulk FinFET Devices
(2008)
Hwang, Chih-Hong
;
Cheng, Hui-Wen
;
Yeh, Ta-Ching
;
Li, Tien-Yeh
;
Huang, Hsuan-Ming
Intrinsic fluctuations on device characteristics, such as the threshold voltage (V(th)) fluctuation is crucial in determining the behavior of nanoscale semiconductor devices. In this paper, the dependency of process-variation and random-dopant-induced Vth fluctuation on the gate oxide thickness scaling in 16 nm metal-oxide-semiconductor field effect transistors (MOSFETs) is investigated. Fluctuations of the threshold voltage for the studied planar MOSFETs with equivalent oxide thicknesses (EOT) from 1.2 nm to 0.2 nm (e.g., SiO(2) for the 1.2 and 0.8 nm EOTs, Al(2)O(3) for the 0.4 nm EOT and HfO(2) for the 0.2 nm EOT) are then for the first time compared with the results of 16nm bulk fin-typed filed effect transistors (FinFETs), which is one of the promising candidates for next generation semiconductor devices. An experimentally validated simulation is conducted to investigate the fluctuation property. Result of this study confirms the suppression of Vth fluctuations with the gate oxide thickness scaling (using high-kappa dielectric). It's found that the immunity of the planar MOSFET against fluctuation suffers from nature of structural limitations. Bulk FinFETs alleviate the challenges of device's scaling and have potential in the nanoelectronics application.

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