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Now showing 1 - 9 of 9
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    Impact of Oxygen Vacancy on the Photo-Electrical Properties of In2O3-Based Thin-Film Transistor by Doping Ga
    (2019-03-01)
    Chen, Kuan-Yu
    ;
    Yang, Chih-Chiang
    ;
    Su, Yan-Kuin
    ;
    Wang, Zi-Hao
    ;
    Yu, Hsin-Chieh
    In this study, amorphous indium gallium oxide thin-film transistors (IGO TFTs) were fabricated by co-sputtering. Three samples with different deposition powers of the In2O3 target, namely, sample A with 50 W deposition power, sample B with 60 W deposition power, and sample C with 70 W deposition power, were investigated. The device performance revealed that oxygen vacancies are strongly dependent on indium content. However, when the deposition power of the In2O3 target increased, the number of oxygen vacancies, which act as charge carriers to improve the device performance, increased. The best performance was recorded at a threshold voltage of 1.1 V, on-off current ratio of 4.5 x 10(6), and subthreshold swing of 3.82 V/dec in sample B. Meanwhile, the optical properties of sample B included a responsivity of 0.16 A/W and excellent ultraviolet-to-visible rejection ratio of 8 x 10(4). IGO TFTs may act as photodetectors according to the results obtained for optical properties.
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    High-performance sidewall damascened tri-gate poly-si TFTs with the strain proximity free technique and stress memorization technique
    (2017-02)
    Hsieh, Dong-Ru
    ;
    Kuo, Po-Yi
    ;
    Lin, Jer-Yi
    ;
    Chen, Yi-Hsuan
    ;
    Chang, Tien-Shun
    In this paper, strained channel-sidewall damascened tri-gate polycrystalline silicon thin-film transistors (SC-SWDTG TFTs) have been successfully fabricated and then demonstrated by an innovative process flow. This process flow without the use of advanced lithography processes combines the sidewall damascened technique (SWDT) and two strain techniques, namely, the strain proximity free technique (SPFT), and the stress memorization technique (SMT), in the poly-Si channels. It has some advantages: (1) the channel shapes and dimensions can be effectively controlled by the wet etching processes and the deposition thickness of the tetraethoxysilane (TEOS) oxide; (2) the source/drain (S/D) resistance can be significantly decreased by the formation of the raised S/D structures; (3) the SPFT, SMT, and the rapid thermal annealing (RTA) treatment can enhance the performance of the SC-SWDTG TFTs without the limitation of the highly scaling stress liner thickness in deep-submicron TFTs. Thus, the SC-SWDTG TFTs exhibit a steep subthreshold swing (S.S.) similar to 110mV/dec., an extremely small drain induced barrier lowing (DIBL) similar to 12.2mVV(-1), and a high on/off ratio similar to 10(7) (V-D = 1V) without plasma treatments for future three-dimensional integrated circuits (3D ICs) applications.
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    Positive gate bias instability alleviated by self-passivation effect in amorphous InGaZnO thin-film transistors
    (2015-12-02)
    Li, GongTan
    ;
    Yang, Bo-Ru
    ;
    Liu, Chuan
    ;
    Lee, Chia-Yu
    ;
    Tseng, Chih-Yuan
    The threshold voltage shift (Delta Vth) under positive gate bias stress (PGBS), generally found in amorphous InGaZnO thin-film transistors (a-IGZO TFTs), has usually been suppressed by external passivation layers. We report it can also be alleviated by the self-passivation effect of the active layer, where moderately increasing the active layer thickness (d(s)) reduces Delta Vth by 82% in SiOx-passivated a-IGZO TFTs. Our experiments in conjunction with simulations show that the instability of V-th comes from ambient factors at the back channel. Larger d(s) results in lower carrier concentrations at the back channel (N-back), fewer diffusive ions affecting the front channel, and much more stable operations under PGBS. The optimal thickness of an IGZO film simultaneously obtaining a small Delta V-th, near-zero Vth, and sharp sub-threshold swing is about 80-90 nm, thicker than those usually adopted. The self-passivation effect combined with the externally deposited passivation layer can improve the overall device reliability.
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    Improving Electrical Performances of p-Type SnO Thin-Film Transistors Using Double-Gated Structure
    (2015-10-01)
    Zhong, Chia-Wen
    ;
    Lin, Horng-Chih
    ;
    Liu, Kou-Chen
    ;
    Huang, Tiao-Yuan
    ;
    電子工程學系及電子研究所
    p-type SnO thin-film transistors (TFTs) using a nominally symmetrical double-gated (DG) structure were studied in this letter. The top and bottom gates can be biased independently (single-gated mode) or jointly to switch the device (DG mode). For the latter operation, it is shown that ON current, subthreshold swing, and OFF-state current of the SnO TFT are all improved as compared with the operations when only one of the two gates is biased. As the device is operated under the DG mode, field-effect mobility of 6.54 cm(2)/V-s, high ON/OFF current ratio of >10(5), and subthreshold swing of 143 mV/decade are obtained. Moreover, the capability of the device in tuning its transfer characteristics under the single-gated operation with the bias applied to the opposite gate is also confirmed.
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    Film-Profile Engineered InGaZnO Thin-Film Transistors With Self-Aligned Bottom Gates
    (2015-08-01)
    Shie, Bo-Shiuan
    ;
    Lin, Horng-Chih
    ;
    Huang, Tiao-Yuan
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    We propose and demonstrate a method which combines film profile engineering (FPE) and a procedure of forming self-aligned bottom gates (SABGs) to fabricate InGaZnO thin-film transistors (TFTs). In the scheme, an ingenious etching procedure was implemented to form the final bottom gate self-aligned to the upper hardmask structure. The fabricated SABG devices show greatly reduced OFF-state leakage as compared with nonself-aligned ones, attributing to the reduction of gate-to-source/drain overlap areas which lowers both parasitic capacitance and gate leakage current. These merits benefit the operation of circuits consisted of TFTs implemented with FPE.
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    Impact of Residual Hardmask Wires on the Performance of Film-Profile-Engineered ZnO Thin-Film Transistors With Discrete Bottom Gates
    (2015-08-01)
    Lyu, Rong-Jhe
    ;
    Lin, Horng-Chih
    ;
    Huang, Tiao-Yuan
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    Root cause for the anomalous degradation in the ON-current of film-profile-engineered ZnO thin-film transistors with discrete bottom gates, a new scheme proposed in our previous work, is investigated. Our findings indicate that the deposited source/drain (S/D) metal contact pads are disconnected owing to two TiN wires hung over the S/D regions, which are unintentionally formed during the fabrication of devices. The disconnected S/D metal contacts cause an increase in the S/D series resistance, and thus, the ON-current is degraded. Several ways for addressing this issue are proposed in this letter, including the simple thinning of gate electrode. As the undesirable TiN wires are eliminated, the devices demonstrate enhanced field-effect mobility and uniformity in performance.
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    奈米碳管網絡薄膜電晶體與奈米碳管網絡導電膜之研究
    (2011)
    崔秉鉞
    ;
    Tsui Bing-Yue
    ;
    國立交通大學電子工程學系及電子研究所
    自從 1991 年Iijima 發現奈米碳管(carbon nanotubes, CNTs)結構之後，由於其具有相當優異的電、 熱、機械、化學性質，吸引了廣泛的注意。單一單壁奈米碳管製作的碳管場效應電晶體應用在電子 工業是一長遠的目標，短期或中期比較可能的應用是利用大量單壁奈米碳管的平均效應來降低元件 間的變異，亦即碳管網絡薄膜電晶體。碳管網絡薄膜電晶體雖然已經有數年的歷史，但是性能尚不 理想。滲濾理論已經證實可以描述碳管網絡的導電能力，善用滲濾理論，搭配適當的製程條件以及 元件結構，有機會得到性能良好的碳管網絡薄膜電晶體。同樣善用滲濾理論，也可以得到導電率良 好的導電薄膜。因此本兩年期計畫預計以高性能的碳管網絡薄膜電晶體與導電膜為研究對象。 第一年度將先以滲濾理論計算碳管長度、密度、元件閘極長度、寬度對臨界長度的關係，據以決 定碳管塗佈的條件，以及元件長度、寬度的設計範圍，然後實際製作元件驗證。本計畫將以旋轉塗佈 方式製作碳管網絡，以符合低溫製程的需求。元件分為兩類，一為碳管網絡薄膜電晶體(CNT NWTFT)，一為碳管網絡導電膜(CNT NWCF)。元件實作將以矽晶片為基板，元件結構以區域性背閘 極結構為主，以簡化製程限制。第二年度計畫重點是將第一年度開發之低溫碳管網絡薄膜電晶體和碳 管網絡導電膜成果應用於透明可撓式基板，實現奈米碳管透明薄膜電晶體。此外，也深入分析碳管網 絡導電膜的可靠度。 本計畫如順利執行，可以建立高良率、開關電流比之碳管網絡透明薄膜電晶體，具軟性電子產業 應用價值。亦可建立碳管網絡導電膜技術，可製作超薄導電薄膜，在特定用途上取代金屬薄膜。在過 程中所研究的課題，包括滲濾理論、載子傳導機制、低溫製程、可撓式基板製程、低溫測試技術、微 區物性/化性分析等等，都具有學術及產業價值。
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    Facile Electroless Deposition of Zinc Oxide Ultrathin Film for Zinc Acetate Solution-processed Transistors
    (2012-07-01)
    Chu, Min-Ching
    ;
    You, Hsin-Chiang
    ;
    Meena, Jagan Singh
    ;
    Shieh, Shao-Hui
    ;
    Shao, Chyi-Yau
    "A low-cost, ultra-thin, transparency and high-quality zinc oxide (ZnO) film was successfully demonstrated as the carrier transporting and semiconducting layer for thin-film transistor (TFT) devices. The ZnO ultra-thin film with 3.7 nm in thickness was spin-coated from zinc acetate sol-gel solution under electroless condition. The film structure was characterized by atomic force microscopy and x-ray diffraction spectroscopy, respectively. Among various processing temperatures, the electrical property of the fabricated TFT verified the devices could be successfully achieved from suitable annealing temperature of 300 to 700 degrees C. However, the higher treatment temperature of 800 to 900 degrees C deteriorated the transistor property due to the loss of oxygen vacancy. The electrical properties of these ZnO-based n-type TFTswere obtained as follows: the mobility (mu(sat))ranged from 0.47 to 1.78 cm(2) V-1 s(-1), the on/off current ratio ranged from 5.7 x 10(5) to 1.6 x 10(6), and the threshold voltage ranged from 9.7 to 17.3 V. The long-term (100 days) characterization for the evaluation of the ultra-thin ZnO TFT reliability on the mobility and on/off current ratio strongly suggested the effectiveness of solution-processed ultra-thin film transistors. This proposed efficient sol-gel solution method to fabricate transparent ZnO ultra-thin film was relatively simple and cost-effective technique, and could be used as a new candidate of material for next-generation electronic devices to meet the growing demand of small feature bioelectronic sensor, light emitting diode and flexible panel."
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    Dynamic negative bias temperature instability in low-temperature poly-Si thin-film transistors
    (2007)
    Chen, Chih-Yang
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    Wang, Tong-Yi
    ;
    Ma, Ming-Wen
    ;
    Chen, Wei-Cheng
    ;
    Lin, Hsiao-Yi
    Dynamic negative bias temperature instability in p-channel low-temperature poly-Si thin-film transistors was studied in this paper. The degradation of the devices was found to be voltage and temperature dependent. In addition, the frequency and duty ratio of the gate pulse affects the degree of the device degradation. The mechanism of the device degradation was investigated, and a physical model is proposed to explain the mechanism.