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Effect of Field Plate on the RF Performance of AlGaN/GaN HEMT Devices
(2012-01-01)
Chiang, Che-Yang
;
Hsu, Heng-Tung
;
Chang, Edward Yi
;
材料科學與工程學系
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Department of Materials Science and Engineering
This paper examines the effect of the field plate structure on the RF performance of AlGaN/GaN High Electron Mobility Transistor (HEMT) devices. While the field plate structure helps to increase the breakdown voltage of the device through modulating the electric field locally, it induces additional feedback capacitance from drain to gate. Such feedback capacitors may impact the overall RF performance of the device especially at high frequencies. Systematic investigations on the small signal as well as power performance as functions of the drain biases are presented. (C) 2011 Published by Elsevier B.V. Selection and/or peer-review under responsibility of Garry Lee
Effective Passivation With High-Density Positive Fixed Charges for GaN MIS-HEMTs
(2017-05-01)
Liu, Shih-Chien
;
Huang, Chung-Kai
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Chang, Chia-Hua
;
Lin, Yueh-Chin
;
Chen, Bo-Yuan
An effective passivation with high-density positive fixed charges was demonstrated on GaN MIS-HEMTs. The positive fixed charges at the interface between passivation and AlGaN surface can reduce the surface potential and expand the quantum well under Fermi level. Besides, to satisfy charge balance, the net charge density at the AlGaN surface must equal to the 2DEG carrier density. Thus, the positive fixed charges passivation can increase the 2DEG carrier density and improve the switching performance of GaN MIS-HEMTs. In this paper, we demonstrated a high-density positive fixed charges (similar to 2.71 x 10(13) e/cm(-2)) passivation using SiON for GaN MIS-HEMTs. The device with SiON passivation exhibits significant improvements in I-V characteristics and dynamic R-ON compared to the conventional SiN passivated device.
Study of the interface stability of the metal (Mo, Ni, Pd)/HfO2/AlN/InGaAs MOS devices
(2017-08-01)
Do, Huy Binh
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Luc, Quang Ho
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Ha, Minh Thien Huu
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Huynh, Sa Hoang
;
Nguyen, Tuan Anh
The degeneration of the metal/HfO2\ interfaces for Mo, Ni, and Pd gate metals was studied in this paper. An unstable PdOx interfacial layer formed at the Pd/HfO2 interface, inducing the oxygen segregation for the Pd/HfO2/InGaAs metal oxide capacitor (MOSCAP). The low dissociation energy for the Pd-O bond was the reason for oxygen segregation. The PdOx layer contains O2- and OH- ions which are mobile during thermal annealing and electrical stress test. The phenomenon was not observed for the (Mo,Ni)/HfO2/InGaAs MOSCAPs. The results provide the guidance for choosing the proper metal electrode for the InGaAs based MOSFET. (C) 2017 Author(s).
Ge/IIIV fin field-effect transistor common gate process and numerical simulations
(2017-04-01)
Chen, Bo-Yuan
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Chen, Jiann-Lin
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Chu, Chun-Lin
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Luo, Guang-Li
;
Lee, Shyong
This study investigates the manufacturing process of thermal atomic layer deposition (ALD) and analyzes its thermal and physical mechanisms. Moreover, experimental observations and computational fluid dynamics (CFD) are both used to investigate the formation and deposition rate of a film for precisely controlling the thickness and structure of the deposited material. First, the design of the TALD system model is analyzed, and then CFD is used to simulate the optimal parameters, such as gas flow and the thermal, pressure, and concentration fields, in the manufacturing process to assist the fabrication of oxide-semiconductors and devices based on them, and to improve their characteristics. In addition, the experiment applies ALD to grow films on Ge and GaAs substrates with three-dimensional (3-D) transistors having high electric performance. The electrical analysis of dielectric properties, leakage current density, and trapped charges for the transistors is conducted by high-and low-frequency measurement instruments to determine the optimal conditions for 3-D device fabrication. It is anticipated that the competitive strength of such devices in the semiconductor industry will be enhanced by the reduction of cost and improvement of device performance through these optimizations. (C) 2017 Society of Photo-Optical Instrumentation Engineers (SPIE).
Suppressing Non-Uniform Tunneling in InAs/GaSb TFET With Dual-Metal Gate
(2016-03-01)
Hsu, Ching-Yi
;
Chang, Chun-Yen
;
Chang, Edward Yi
;
Hu, Chenming
;
材料科學與工程學系
Non-uniformity in electric field causes early onset of tunneling near the edge of InAs/GaSb hetero-junction tunneling field-effect transistors. When a small area, often an edge, of the tunneling junction has a lower turn-on voltage, the steep switching characteristic is degraded. Fermi pinning at InAs surface greatly worsen the uniformity. We propose a dual-metal gate structure to address the non-uniformity issue. With proper choice of work functions, the dual-metal gate structure can effectively suppress the early onset of edge tunneling and significantly improve the subthreshold swing.
Efficiency Enhancement of Multicrystalline Silicon Solar Cells by Inserting Two-Step Growth Thermal Oxide to the Surface Passivation Layer
(2017-01-01)
Liao, Shun Sing
;
Lin, Yueh Chin
;
Chuang, Chuan Lung
;
Chang, Edward Yi
;
材料科學與工程學系
In this study, the efficiency of the multicrystalline was improved by inserting a two-step growth thermal oxide layer as the surface passivation layer. Two-step thermal oxidation process can reduce carrier recombination at the surface and improve cell efficiency. The first oxidation step had a growth temperature of 780 degrees C, a growth time of 5 min, and with N-2/O-2 gas flow ratio 12 : 1. The second oxidation had a growth temperature of 750 degrees C, growth time of 20 min, and under pure N-2 gas environment. Carrier lifetime was increased to 15.45 mu s, and reflectance was reduced 0.52% using the two-step growth method as compared to the conventional one-step growth oxide passivation method. Consequently, internal quantum efficiency of the solar cell increased 4.1%, and conversion efficiency increased 0.37%. These results demonstrate that the two-step thermal oxidation process is an efficient way to increase the efficiency of the multicrystalline silicon solar cells.
Direct growth of a 40 nm InAs thin film on a GaAs/Ge heterostructure by metalorganic chemical vapor deposition
(2014-09-01)
Yu, Hung-Wei
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Wang, Tsun-Ming
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Nguyen, Hong-Quan
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Wong, Yuen-Yee
;
Tu, Yung-Yi
In this paper, the authors directly grew an InAs thin film (40 nm) by metalorganic chemical vapor deposition on GaAs/Ge substrates by using flow-rate modulation epitaxy with an appropriate V/III ratio. The growth of a high-quality InAs thin film with periodic 90 degrees misfit dislocations was related to a uniform monolayer In atom distribution at the InAs/GaAs interface. The In monolayer effectively minimized the difference between surface energy and strain energy, producing a stable interface during material growth. The authors also found that a tightly controlled V/III ratio can improve the quality of the InAs islands on the GaAs/Ge heterostructures, though it is not the key factor in InAs thin-film growth. (C) 2014 American Vacuum Society.
Evaluation and Reliability Assessment of GaN-on-Si MIS-HEMT for Power Switching Applications
(2017-02-01)
Chou, Po-Chien
;
Chen, Szu-Hao
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Hsieh, Ting-En
;
Cheng, Stone
;
del Alamo, Jesus A.
This paper reports an extensive analysis of the physical mechanisms responsible for the failure of GaN-based metal-insulator-semiconductor (MIS) high electron mobility transistors (HEMTs). When stressed under high applied electric fields, the traps at the dielectric/III-N barrier interface and inside the III-N barrier cause an increase in dynamic on-resistance and a shift of threshold voltage, which might affect the long term stability of these devices. More detailed investigations are needed to identify epitaxy- or process-related degradation mechanisms and to understand their impact on electrical properties. The present paper proposes a suitable methodology to characterize the degradation and failure mechanisms of GaN MIS-HEMTs subjected to stress under various off-state conditions. There are three major stress conditions that include: V-DS = 0 V, off, and off (cascode-connection) states. Changes of direct current (DC) figures of merit in voltage step-stress experiments are measured, statistics are studied, and correlations are investigated. Hot electron stress produces permanent change which can be attributed to charge trapping phenomena and the generation of deep levels or interface states. The simultaneous generation of interface (and/or bulk) and buffer traps can account for the observed degradation modes and mechanisms. These findings provide several critical characteristics to evaluate the electrical reliability of GaN MIS-HEMTs which are borne out by step-stress experiments.
Gold-Free Fully Cu-Metallized InGaP/InGaAs/Ge Triple-Junction Solar Cells
(2014-12-01)
Hsu, Ching-Hsiang
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Chang, Edward Yi
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Chang, Hsun-Jui
;
Yu, Hung-Wei
;
Hong Quan Nguyen
Copper contacts and interconnects were developed for GaAs and Ge for low-cost solar cell application. In addition, thermally annealed Pd/Ge and Pt/Ti/Pt metallizations were created for ohmic contacts to n-GaAs and p-Ge with contact resistance of 4.4 x 10(-6) and 6.9 x 10(-6) Omega cm(2), respectively. Utilizing such metallization structure for InGaP/InGaAs/Ge triple-junction device structure solar cells were fabricated that delivered conversion efficiency of 23.11%, which is average efficiency for the above device structure.
Investigation of the low-temperature AlGaN interlayer in AlGaN/GaN/AlGaN double heterostructure on Si substrate
(2014-11-01)
Hsiao, Yu-Lin
;
Wang, Yi-Jie
;
Chang, Chia-Ao
;
Weng, You-Chen
;
Chen, Yen-Yu
A low-temperature (LT) AlGaN interlayer is inserted in the Al0.1Ga0.9N back barrier layer of an Al0.2Ga0.8N/GaN/Al0.1Ga0.9N double heterostructure grown on a 150mm Si substrate. It is found that the 21-nm-thick LT-AlGaN interlayer plays an important role in stress relaxation and dislocation reduction of the Al0.1Ga0.9N back barrier layer, especially for screw dislocation reduction. In addition, a buffer breakdown voltage higher than 600V is achieved, which is much higher than those of conventional heterostructures. These results demonstrate the effectiveness of combining the LT-AlGaN interlayer and the Al0.2Ga0.8N/GaN/Al0.1Ga0.9N double heterostructure on a Si substrate to increase the breakdown voltage for high-power applications. (C) 2014 The Japan Society of Applied Physics

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