學術出版;;Publications

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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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Now showing 1 - 9 of 9

A 2-V 2-GHz BJT variable frequency oscillator
(1998-09-01)
Chen, WZ
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new LC-tuned negative-resistance variable-frequency oscillator (VFO) is described. Frequency tuning is accomplished by using a variable-impedance converter (VIC) to simulate the varactor function, A negative-impedance converter provides the necessary negative resistance for oscillation and also functions as the voltage level shifters for the VIC. A low-voltage translinear circuit is used to linearize the tuning characteristic of the VFO. Implemented in a 0.8 mu m 12 GHz f(T) BiCMOS technology, the VFO has a tuning range from 1.55 to 2.02 GHz, while consuming 15 mA from a -2 V supply.
A 2-V, 1.8-GHz BJT phase-locked loop
(1999-06-01)
Chen, WZ
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper describes the design of a bipolar junction transistor phase-locked loop (PLL) for Sigma Delta fractional-N frequency-synthesis applications. Implemented in a 0.8-mu m BICMOS technology, the PLL can operate up to 1.8 GHz while consuming 225 mW of power from a single -2-V supply. The entire LC-tuned negative-resistance variable-frequency oscillator is integrated on the same chip. A differential low-voltage current-mode logic circuit configuration is used in most of the PLL's functional blocks to minimize phase jitter and achieve low-voltage operation. The multimodulus frequency divider is designed to support multibit digital modulation. The new phase and frequency detector and loop filter contain only npn transistors and resistors and thus achieve excellent resolution in phase comparison. When phase locked to a 53.4-MHz reference clock, the measured phase noise of the 1.6-GHz output is -91 dBc/Hz at 10-kHz offset, The frequency switching time from 1.677 to 1.797 GHz is 150 mu s. Die size is 4300 x 4000 mu m(2), including the passive loop filter.
Phenanthrenequinone-doped poly(methyl methacrylate) photopolymer bulk for volume holographic data storage
(2000-04-01)
Lin, SH
;
Hsu, KY
;
Chen, WZ
;
Whang, WT
;
材料科學與工程學系
We present the design and fabrication of a phenanthrenequinone-doped poly(methyl methacrylate) photopolymer material. Large blocks of samples were made, and the material showed negligible shrinkage after optical exposures. We recorded and reconstructed 250 holograms at a single spot, using a 1-cm(3) block. (C) 2000 Optical Society of America OCIS codes: 210.2860, 210.4810, 160.5470.
Comparison of the recording dynamics of phenanthrenequinone-doped poly(methyl methacrplate) materials
(2001-07-01)
Mumbru, J
;
Solomatine, I
;
Psaltis, D
;
Lin, SH
;
Hsu, KY
A comparative analysis of phenanthrenequinone-doped poly(methyl methacrylate) materials fabricated at California Institute of Technology and National Chiao Tung University is performed in order to understand the differences exhibited in their recording and baking dynamics. (C) 2001 Published by Elsevier Science B.V.
A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-mu m digital CMOS process
(2004-01-01)
Chen, WZ
;
Chang, JX
;
Hong, YJ
;
Wong, MT
;
Kuo, CL
This brief describes the design of a frequency synthesizer for 2.3/4.6-GHz wireless applications in a 0.35-mum digital CMOS process. This synthesizer provides dual-band output signals by means of frequency doubling techniques. Output frequency of the proposed synthesizer ranges from 1.87-2.3 GHz, and 3.74-4.6 GHz. This chip consumes a total power of 80 mW from a single 2-V supply, including 45 mW for dual-band output buffers. Core size is 2200 mum x 1600 mum.
Holographic data storage using photopolymer
(1999)
Hsu, KY
;
Lin, SH
;
Whang, WT
;
Chen, WZ
;
光電工程學系
We present our studies on a photopolymer of poly(methyl methacrylate) (PMMA) doped with phenathrenequinone (PQ) molecules. We describe their characteristics for holographic data storage, including photo-sensitivity, material M/#, angular selectivity, dynamic exposure schedule, absorption and scattering effect. Experimental demonstrations on multiple digital data pages stored in a polymer cube are presented.
Exposure schedule for multiplexing holograms in photopolymer
(1999)
Lin, SAH
;
Hsu, KY
;
Chen, WZ
;
Whang, WT
;
光電工程學系
We present dynamics of the grating formation process in phenanthrenequinone- (PQ-) doped poly(methyl methacrylate) (PMMA) photo-polymer. The exposure schedule for multiplexing holograms to achieve equal-strength storage in a single location is described. The analysis method is valid for any saturated media, thus the results can be applied to other photo-polymer materials with similar kinetics.
A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end
(2005-06-01)
Chen, WZ
;
Cheng, YL
;
Lin, DS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-mu m CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV((pp)). In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dB Omega and -3 dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12 dBm at a bit-error rate of 10(-12) with a 2(31) -1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 mu m x 1796 mu m.
Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-mu m digital CMOS technology
(2006-05-01)
Chen, WZ
;
Lu, CH
;
電子工程學系及電子研究所
;
Innovative Packaging Research Center
;
Department of Electronics Engineering and Institute of Electronics
This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabricated in a low-cost 0.35-mu m digital CMOS process, this integrated circuit integrates both transimpedance amplifier and post limiting amplifier on a single chip. In order to facilitate high-speed operations in a low-cost CMOS technology, the receiver front-end has been designed utilizing several enhanced bandwidth techniques, including inductive peaking and current injection. Moreover, a power optimization methodology for a multistage wide band amplifier has been proposed. The measured input-referred noise of the optical receiver is about 0.8 mu A(rms). The input sensitivity of the receiver front-end is 16 mu A for 2.5-Gbps operation with bit-error rate less than 10(-12), and the output swing is about 250 mV (single-ended). The front-end circuit drains a total current of 33 mA from a 3-V supply. Chip size is 1650 mu m x 1500 mu m.

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