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A novel two-step etching to suppress the charging damages during metal etching employing helicon wave plasma
(1998-06-01)
Cheng, HC
;
Lin, W
;
Kang, TK
;
Perng, YC
;
Dai, BT
A two-step etching has been performed to eliminate the plasma charging damages during helicon-wave plasma metal etching without selectivity loss, This technique utilized a normal etching recipe to remove the Al film and followed by an optimized etching recipe for the overetching step. By increasing the bias power and decreasing the source power, the optimum etching recipe can cause the plasma more directionally and reduce the Al charging damages. Eventually, the damage mechanism was also reported.
Effects of helicon-wave-plasma etching on the charging damage of aluminum interconnects
(1998-07-01)
Lin, W
;
Kang, TK
;
Perng, YC
;
Dai, BT
;
Cheng, HC
The etching parameters of aluminum in the helicon wave plasma are characterized to elucidate the mechanism of charging damage. By increasing the ion energy and decreasing the plasma density via increase of the bias power and decrease of the source power, respectively, we can significantly reduce charging damage, On the basis of this concept, we develop a two-step etching technique to suppress the charging damage without selectivity loss. Such a high-density plasma etching technique will be very suitable for the formation of high-density, and narrow-line interconnects.
A novel process to form cobalt silicided p(+) poly-Si gates by BF2+ implantation into bilayered CoSi/a-Si films and subsequent anneal
(1998-07-01)
Lai, WK
;
Liu, HW
;
Juang, MH
;
Chen, NC
;
Cheng, HC
A novel process that implants BF2+ ions into thin bilayered CoSi/a-Si films has been shown to form cobalt silicided pf poly-Si gates with excellent gate oxide integrity and very small flatband shift. The effects of not only using the CoSi layer as an implantation barrier but also keeping the a-Si underlayer during the initial silicide formation both significantly suppress the boron penetration through thin gate oxide.
Excellent low-pressure-oxidized Si3N4 films on roughened poly-si for high-density DRAM's
(1998-09-01)
Liu, HW
;
Cheng, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
High-reliability and good-performance stacked storage capacitors with high capacitance value of 17.8 fF/mu m(2) has been realized using low-pressure-oxidized thin nitride films deposited on roughened poly-Si electrodes. This novel electrodes are fabricated by H3PO4-etched and RCA-cleaned. The leakage current density at +2.5 and -2.5 V are 9.07 x 10(-9) and -2.4 x 10(-8) A/cm(2), respectively, fulfilling the requirements of 256 Mb DRAM's. Weibull plots of time-dependent-dielectric-breakdown (TDDB) characteristics under constant current stress and constant voltage stress also show tight distribution and good electrical properties. Hence, this easy and simple technique is promising for future high-density DRAM's applications.
Effects of CoSi2 on p(+) polysilicon gates fabricated by BF2+ implantation into CoSi amorphous Si bilayers
(1998-10-01)
Cheng, HC
;
Lai, WK
;
Liu, HW
;
Juang, MH
;
電子工程學系及電子研究所
The integrity of thin gate oxide structures fabricated by implanting BF2+ ions into bilayered CoSi/amorphous silicon films and subsequent annealing has been studied as a function of cobalt silicide thickness and implantation energy. Significant degradation of gate oxide integrity and flatband voltage shifts were found with increasing cobalt silicide thickness and annealing temperature. It is shown that although thinner cobalt silicide can result in excellent gate dielectric integrity it also leads to worse thermal stability at a high annealing temperature. Moreover, shallower implantation depth and lower annealing temperature can reduce the boron penetration, but depletion effects in polycrystalline silicon gates are caused accordingly. Hence, appropriate process conditions, involving trade-offs among CoSi2 thickness, implantation energy and annealing temperature, must be used to optimize the device performance while retaining the thin dielectric reliability.
Effects of O-2- and N2O-plasma treatments on properties of plasma-enhanced-chemical-vapor-deposition tetraethylorthosilicate oxide
(1999-07-01)
Chen, YC
;
Yang, MZ
;
Tung, IC
;
Chen, MP
;
Feng, MS
The high quality silicon oxide films were prepared by plasma-enhanced chemical vapor deposition (PECVD) using tetraethylorthosilicate (TEOS)-oxygen based chemistry. The O-2- or N2O-plasma treatments were performed on the as-deposited films as an attempt to improve the properties of the TEOS oxide films. TEOS oxide film deposited at lower pressure had lower Si-OH content, less carbon impurity, and flatter surface, and hence had better electrical properties. Both O-2- and N2O-plasma would decrease the oxygen content of the oxide film, which led the composition of the film to deviate from the stoichiometric SiO2. The O-2-plasma treatment did not show the encouraging effect on the chemical structure and electrical properties of the TEOS oxide films. In contrast, the N2O-plasma treatment could be a promising means to improve the breakdown field and leakage current density of the TEOS oxide films, which was accomplished by the N2O-plasma effect to facilitate the passivation of dangling bonds, linking reaction of Si-OH bonds, nitridation reaction and densification of the amorphous silicon oxide network.
Effects of rapid thermal annealing on cobalt silicided p(+) poly-Si gates fabricated by BF2+ implantation into bilayered CoSi/a-Si films
(1999-07-01)
Lai, WK
;
Liu, HW
;
Juang, MH
;
Cheng, HC
;
電子工程學系及電子研究所
The cobalt polycide gate formed by implanting BF2+ ions into the bilayered CoSi/a-Si films and the subsequent rapid thermal anneal has been studied. The resulting gate oxide integrity is characterized with respect to various silicide thicknesses and implantation energies. Significant degradation in gate oxide integrity and Aat-band voltage shift were found with increasing silicide thickness and annealing temperature, especially for the thicker CoSi2 films, which is attributable to severe boron penetration. Although a thinner silicide can achieve excellent gate dielectric reliability, it will lead to poor high-temperature thermal stability. Moreover, shallower implantation depth and lower annealing temperature, which sustain less boron penetration, would cause the poly-Si gate depletion effects. Therefore, appropriate conditions, which comprise the CoSi2 thickness, the implantation energy, and the annealing temperature, should be employed to optimize the device performance while retaining the thin dielectric reliability.
Suppression of boron penetration for p(+) stacked poly-Si gates by using inductively coupled N-2 plasma treatment
(1999-10-01)
Cheng, HC
;
Lai, WK
;
Hwang, CC
;
Juang, MH
;
Chu, SC
Nitridation of the stacked poly-Si gates by the inductively coupled N-2 plasma (ICNP) treatments has been shown to suppress the boron penetration and improve the gate oxide integrity. The ICNP treatments on the stacked poly-Si layers would create the nitrogen-rich layers not only between the stacked poly-Si layers but also in the gate oxide after post implant anneal, thus resulting in effective retardation of boron diffusion. In addition, the position of ICNP treatment closer to gate oxides leads to higher nitrogen peaks in the gate oxide region, resulting in further suppression of boron penetration and improvement of gate oxide reliability.
Thin-film transistors with polycrystalline silicon films prepared by two-step rapid thermal annealing
(2000-01-15)
Cheng, HC
;
Huang, CY
;
Wang, FS
;
Lin, KH
;
Tarntair, FG
A novel two-step rapid thermal annealing (RTA) process has been developed to significantly reduce the crystallization time for the solid-phase crystallization (SPC) of amorphous silicon films. In comparison with the conventional SPC processes, it not only keeps a low thermal budget but also achieves a larger poly-Si film grain size than that obtained by one-step RTA, and even as large as that obtained by conventional furnace annealing (CFA). Furthermore, poly-Si thin-film transistors fabricated by such a novel annealing scheme possess electrical characteristics superior to those obtained by one-step RTA and comparable to those obtained by long-time CFA.
Fabrication and characterization of various carbon-clad silicon microtips with ultra-small tip radii
(2000-02-01)
Tarntair, FG
;
Hong, WK
;
Ku, TK
;
She, NJ
;
Chen, CF
Various types of ultra sharp Si microtips and multitips with carbon-clading films were fabricated by microwave plasma chemical vapor deposition (MPCVD). The radii of these Si tips prepared by bias assisted carburization (BAC) can he reduced below 300 Angstrom under a low deposition temperature (<550 degrees C). Field emission characterization was performed in a high vacuum environment. With an applied anode voltage of 1100 V, emission currents of 169 mu A, 198 mu A, and 385 mu A can be achieved from an array of 50 x 50 BAG-clad Si monotips, Si multitips via high bias, and Si multitips via the Ar presputtering technique, respectively. Both the auger electron spectroscopy (AES) and X-ray photo-electron spectroscopy (XPS) studies of the C l s peak suggest that the BAC-cladding is more likely to be a carbon-rich SiC layer or a SiC layer mixed with a small amount of diamond nuclei. This BAC-carbon can be used as an effective nucleation layer for further diamond nuclei. Due to the low field emission, low temperature, and large area growth capability, the sharp BAC-clad Si multitip field emitter arrays are attractive Tor flat panel display applications.

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