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Now showing 1 - 10 of 79

Remarkably high mobility ultrathin-film metal-oxide transistor with strongly overlapped orbitals
(2016-01-08)
Shih, Chen Wei
;
Chin, Albert
;
Lu, Chun Fu
;
Su, Wei Fang
;
電子工程學系及電子研究所
High mobility channel thin-film-transistor (TFT) is crucial for both display and future generation integrated circuit. We report a new metal-oxide TFT that has an ultra-thin 4.5 nm SnO2 thickness for both active channel and source-drain regions, very high 147 cm(2)/Vs field-effect mobility, high I-ON/I-OFF of 2.3 x 10(7), small 110 mV/dec sub-threshold slope, and a low V-D of 2.5V for low power operation. This mobility is already better than chemical-vapor-deposition grown multi-layers MoS2 TFT. From first principle quantum-mechanical calculation, the high mobility TFT is due to strongly overlapped orbitals.
Remarkably High Mobility Thin-Film Transistor on Flexible Substrate by Novel Passivation Material
(2017-04-25)
Shih, Cheng Wei
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
High mobility thin-film transistor (TFT) is crucial for future high resolution and fast response flexible display. Remarkably high performance TFT, made at room temperature on flexible substrate, is achieved with record high field-effect mobility (mu(FE)) of 345 cm(2)/Vs, small sub-threshold slope (SS) of 103 mV/dec, high on-current/off-current (I-ON/I-OFF) of 7 x 10(6), and a low drain-voltage (V-D) of 2 V for low power operation. The achieved mobility is the best reported data among flexible electronic devices, which is reached by novel HfLaO passivation material on nano-crystalline zinc-oxide (ZnO) TFT to improve both I-ON and I-OFF. From X-ray photoelectron spectroscopy (XPS) analysis, the non-passivated device has high OH-bonding intensity in nano-crystalline ZnO, which damage the crystallinity, create charged scattering centers, and form potential barriers to degrade mobility.
High Performance Metal-Gate/High-kappa GaN MOSFET With Good Reliability for Both Logic and Power Applications
(2016-09-01)
Yi, Shih-Han
;
Ruan, Dun-Bao
;
Di, Shaoyan
;
Liu, Xiaoyan
;
Wu, Yung Hsien
The gate-recessed GaN MOSFET on a Si substrate is demonstrated to achieve a record highest normalized transistor current (mu C-ox) of 335 mu A/V-2 (410 mA/mm at L-G = 5 mu m and only V-G = 4 V), I-ON/I-OFF of 9 orders of magnitude, small 79 mV/dec sub-threshold slope, a low oxide/GaN interface trap density of 1.2 x 10(10) eV(-1)/cm(2), a low on-resistance of 17.0 Omega-mm, a high breakdown voltage of 720-970 V, and excellent reliability of only 40 mV Delta V-T after 175 degrees C 1000 s stress at maximum drive current. Such excellent device integrities are due to the high-kappa gate dielectric and the high conduction band offset (Delta E-C) of SiO2/GaN. From the calculation results of self-consistent Schrodinger and Poisson equations, the good reliability of GaN MOSFET is related to the confined carrier density within the GaN channel, which is in sharp contrast to the strong wave-function penetration into the high-trap density AlGaN barrier in the AlGaN/GaN HEMT.
Foreword Special Issue on Advanced Technology for Ultra-Low Power Electronic Devices
(2016-09-01)
Berger, Paul R.
;
Chin, Albert
;
Nishiyama, Akira
;
Ieong, Meikei
;
交大名義發表
A Novel Read Scheme for Large Size One-Resistor Resistive Random Access Memory Array
(2017-02-10)
Zackriya, Mohammed, V
;
Kittur, Harish M.
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The major issue of RRAM is the uneven sneak path that limits the array size. For the first time record large One-Resistor (1R) RRAM array of 128x128 is realized, and the array cells at the worst case still have good Low-/High-Resistive State (LRS/HRS) current difference of 378 nA/16 nA, even without using the selector device. This array has extremely low read current of 9.7 mu A due to both low-current RRAM device and circuit interaction, where a novel and simple scheme of a reference point by half selected cell and a differential amplifier (DA) were implemented in the circuit design.
Ferroelectric thin film processing for ferroelectric field-effect transistor
(2003-12-04)
Chen, San-Yuan
;
Chin, Albert
;
Sun, Chia-Liang
The present invention relates to a method for manufacturing a ferroelectric field-effect transistor, particularly to a ferroelectric field-effect transistor with a metal/ferroelectric/insulator/semiconductor (MFIS) gate capacitor structure. The method comprises steps of depositing a bismuth layered ferroelectric film on the insulator buffered Si, after a high-temperature thermal treatment, depositing an upper electrode on the bismuth layered ferroelectric film.
Method for making very low Vt metal-gate/high-k CMOSFETs using self-aligned low temperature shallow junctions
(2009-11-12)
Chin, Albert
This invention proposes a method for making very low threshold voltage (Vt) metal-gate/high-κ CMOSFETs using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with VLSI. At 1.2 nm equivalent-oxide thickness (EOT), good effective work-function of 5.3 and 4.1 eV, low Vt of +0.05 and 0.03 V, high mobility of 90 and 243 cm2/Vs, and small 85° C. bias-temperature-instability<32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.
A Low-Power K-Band CMOS VCO With Four-Coil Transformer Feedback
(2010-08-01)
Liu, Szu-Ling
;
Chen, Kuan-Han
;
Chang, Tsu
;
Chin, Albert
;
電子工程學系及電子研究所
A K-band low-power and low-phase-noise voltagec-ontrolled oscillator (VCO) is presented in this letter. By utilizing four-coil transformer feedback and forward body bias topology, good performances are obtained under a low-power supply with a 5.1% tuning range and a phase noise of -109.8 dBc/Hz at 1 MHz offset from the 21.37-GHz carrier frequency. The core circuit of this VCO only consumes 3.5 mW with a 0.6-V supply voltage and a 0.55-V body bias.
Ultralow-Power Ni/GeO/STO/TaN Resistive Switching Memory
(2010-09-01)
Cheng, C. H.
;
Chin, Albert
;
Yeh, F. S.
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Using novel stacked covalent-bond-dielectric GeO(x) (GeO) on metal-oxide SrTiO(3) to form a cost-effective Ni/GeO/SrTiO/TaN resistive switching memory, an ultralow set power of small 4 mu W (3.5 mu A at 1.1 V), a reset power of 16 pW (0.12 nA at 0.13 V), and a large 10(6) memory window for 10(5)-s retention at 85 degrees C are realized for the first time. A positive temperature coefficient is measured at low-resistance state and different from the metallic filament in metal-oxide resistive random access memory.
Highly scaled charge-trapping layer of ZrON nonvolatile memory device with good retention
(2010-11-22)
Tsai, C. Y.
;
Lee, T. H.
;
Cheng, C. H.
;
Chin, Albert
;
Wang, Hong
We have fabricated the TaN-[SiO(2)-LaAlO(3)]-ZrON-[LaAlO(3)-SiO(2)]-Si charge-trapping flash device with highly scaled 3.6 nm equivalent-Si(3)N(4)-thickness. This device shows large 4.9 V initial memory window, and good retention of 3.4 V ten-year extrapolated retention window at 85 degrees C, under very fast 100 mu s and low +/- 16 V program/erase. These excellent results were achieved using deep traps formed in ZrON trapping layer by As(+) implantation that was significantly better than those of control device without ion implantation. (C) 2010 American Institute of Physics. [doi:10.1063/1.3522890]

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