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Access type: Open accessAuthor: search.filters.author.Kuo, Ming-Ching

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Now showing 1 - 6 of 6
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    A 340 GHz Triple-Push Oscillator With Differential Output in 40 nm CMOS
    (2014-12-01)
    Li, Chun-Hsing
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    Ko, Chun-Lin
    ;
    Kuo, Chien-Nan
    ;
    Kuo, Ming-Ching
    ;
    Chang, Da-Chiang
    A low-power triple-push oscillator with differential output is proposed in this letter. By extracting signals from the same current loop, the oscillator can naturally provide differential output without any additional active circuit or passive balun required. Therefore, the output power can be increased and the chip area and power consumption can be reduced. Realized in 40 nm CMOS technology, the proposed oscillator can oscillate at 340.6 GHz while providing equivalent isotropically radiated power (EIRP) as -21.8 dBm. The power consumption is only 34.1 mW from a 0.9 V supply. The oscillator core only occupies area of 0.028 mm(2).
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    A Low-Cost DC-to-84-GHz Broadband Bondwire Interconnect for SoP Heterogeneous System Integration
    (2013-12-01)
    Li, Chun-Hsing
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    Ko, Chun-Lin
    ;
    Kuo, Chien-Nan
    ;
    Kuo, Ming-Ching
    ;
    Chang, Da-Chiang
    A low-cost broadband bondwire interconnect is proposed for heterogeneous system integration. Transmission lines are incorporated with bondwires to form a two-path structure, which can effectively reduce the bondwire effect. Theoretical analysis is provided using a graphical method and it shows that the interconnect can give widest operation bandwidth from dc up to a maximum frequency f(max) if the length of the transmission lines is designed at an optimal electrical length theta(max) . In particular, theta(max) only depends on the characteristic impedance of the transmission lines. The achievable f(max) is limited by the bondwire inductance, i.e., smaller bondwire inductance is preferred to have wider operation bandwidth. An interconnect from a 0.18-mu m CMOS chip to a glass-integrated-passive-device carrier is designed to verify the proposed concept. Measured results show that the insertion loss and the return loss can be better than 3.0 and 13.4 dB, respectively, from dc to 84 GHz. The proposed interconnect shows around 3.2 times bandwidth of a single bondwire alone. To the best of authors' knowledge, this work demonstrates the bondwire interconnect with the widest operation bandwidth for heterogeneous system integration by using system-on-package reported thus far.
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    A 210-GHz Amplifier in 40-nm Digital CMOS Technology
    (2013-06-01)
    Ko, Chun-Lin
    ;
    Li, Chun-Hsing
    ;
    Kuo, Chien-Nan
    ;
    Kuo, Ming-Ching
    ;
    Chang, Da-Chiang
    This paper presents a 210-GHz amplifier design in 40-nm digital bulk CMOS technology. The theoretical maximum voltage gain that an amplifier can achieve and the loss of a matching network are derived for the optimization of a few hundred gigahertz amplifiers. Accordingly, the bias and size of transistors, circuit topology, and inter-stage coupling method can be determined methodically to maximize the amplifier gain. The measured results show that the amplifier exhibits a peak power gain of 10.5 dB at 213.5 GHz and an estimated 3-dB bandwidth of 13 GHz. The power consumption is only 42.3 mW under a 0.8-V supply. To the best of the authors' knowledge, this work demonstrates the CMOS amplifier with highest operation frequency reported thus far.
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    A 1.2-V 5.2-mW 20-30-GHz Wideband Receiver Front-End in 0.18-mu m CMOS
    (2012-11-01)
    Li, Chun-Hsing
    ;
    Kuo, Chien-Nan
    ;
    Kuo, Ming-Ching
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This paper presents a low-power wideband receiver front-end design using a resonator coupling technique. Inductively coupled resonators, composed of an on-chip transformer and parasitic capacitances from a low-noise amplifier, a mixer, and the transformer itself, not only provide wideband signal transfer, but also realize wideband high-to-low impedance transformation. The coupled resonators also function as a wideband balun to give single-to-differential conversion. Analytic expressions for the coupled resonators with asymmetric loads are presented for design guidelines. The proposed receiver front-end only needs a few passive components so that gain degradation caused by the passive loss is minimized. Hence, power consumption and chip area can be greatly reduced. The chip is implemented in 0.18-mu m CMOS technology. The experimental result shows that the -3-dB bandwidth can span from 20 to 30 GHz with a peak conversion gain of 18.7 dB. The measured input return loss and third-order intercept point are better than 16.7 dB and -7.6 dBm, respectively, over the bandwidth. The minimum noise figure is 7.1 dB. The power consumption is only 5.2 mW from a 1.2-V supply. The chip area is only 0.18 mm(2).
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    A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13 mu m CMOS
    (2009-03-01)
    Kuo, Ming-Ching
    ;
    Kao, Shiau-Wen
    ;
    Chen, Chih-Hung
    ;
    Hung, Tsun-Shuen
    ;
    Shih, Yi-Shing
    A fully integrated direct-conversion tuner is implemented in 0.13 mu m CMOS technology. A broadband noise-canceling balun LNA with the proposed dual cross-coupling technique helps achieve an overall receiver noise figure from 3.7 to 4.3 dB while consuming only 3.6 mW. The proposed current-mode switching scheme improves the achievable SNIR with a gain step of 15 dB, providing IIP3 improvement of 18 dB and NF degradation of only 6 dB. Moreover, design trade-offs are carefully considered in designing the baseband circuit, which provides wide gain tuning and bandwidth accuracy with a DC offset residual less than 6 mV. The measured maximum SNR values are better than 30 dB over wide input power levels, ensuring robust reception in a mobile environment. All circuit blocks are operated at 1.2 V. As a result, the tuner consumes power as low as 114 mW in the continuous mode. This compact tuner supports both UHF and L-bands, and occupies only 7.2 mm(2) die area.
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    Wideband LNA Compatible for Differential and Single-Ended Inputs
    (2009-07-01)
    Kuo, Ming-Ching
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    Kuo, Chien-Nan
    ;
    Chueh, Tzu-Chan
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    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This letter presents a wideband low-noise amplifier (LNA) that supports both differential and single-ended inputs, while providing differential output. The LNA is implemented in 0.13 mu m. CMOS technology. For sub-1 GHz wideband applications, this LNA achieves 22.5 dB voltage gain, +1 dBrn IIP3, and 2.5 dB NF in the differential receiving mode, while achieving 23 dB voltage gain, -0.5 dB m IIP3, and 2.65 dB NF in the single-ended receiving mode. The LNA core circuit draws 2.5 mA from 1.2 V supply voltage, and occupies a small chip area of 0.06 mm(2).