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Integrating passive components with active circuits using standard silicon process for millimeter-wave applications - (Invited paper)
(2008)
Meng, Chinchun
;
Tseng, Sheng-Che
;
電信工程研究所
;
Institute of Communications Engineering
Several passive components based on the quarter-wavelength transmission line can be integrated with active circuits for millimeter-wave applications. Passive components such as Marchand baluns, quadrature couplers, and rat-race hybrids are directly implemented on the standard low-resisitivity (similar to 10 Omega- cm) silicon substrate. New circuit design concepts such as balanced loss and distortionless transmission line are applied to tolerate the unavoidable loss and thus the size reduction is achieved because of the high effective dielectric constant.
A 2.4-GHz Low-Flicker-Noise CMOS Sub-Harmonic Receiver
(2013-02-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
Wang, Chia-Ling
;
電機工程學系
;
Department of Electrical and Computer Engineering
A 2.4-GHz low-noise sub-harmonic direct-conversion receiver (SH-DCR) is demonstrated using standard 0.18-mu m CMOS technology. Deep-n-well vertical-NPN (V-NPN) bipolar junction transistors (BJTs) are employed to solve the flicker noise problem in CMOS process. Design optimization of a power-constrained noise-impedance-matched low-noise amplifier (LNA) with the effect of lossy on-chip inductors is fully discussed in this paper. A multi-stage octet-phase polyphase filter is analyzed in detail and implemented to generate well balanced octet-phase LO signals. As a result, the demonstrated receiver achieves 51-dB voltage gain and 3-dB noise figure with flicker noise corner less than 30 kHz when RF = 2.4 GHz. The I/Q amplitude/phase mismatch is below +/-0.2 dB/+/-1 degrees, respectively, covering from 2.35 to 2.6 GHz. The dc current consumption is 5 mA at a 1.8-V supply.
2.4/5.7-GHz Dual-Band Dual-Conversion Architecture With Correlated LO Signal Generators
(2009)
Syu, Jin-Siang
;
Meng, Chinchun
;
Yu, Sheng-Wen
;
Wu, Tzung-Han
;
Huang, Guo-Wei
A 2.4/5.7-GHz dual-band dual-conversion downconverter is demonstrated using 0.35-mu m SiGe hetero-junction bipolar transistor (HBT) technology. This downconverter employs a complex dual-conversion system and a complex filter to reject the first and second image signals, respectively. The LO(1) frequency is 2.5 times the LO(2) frequency and is generated by a divide-by-two divider, a frequency doubler and a single-sideband up-converter. As a result, the correlated LO signals maintain excellent image-rejection performance of the dual-conversion system while only one LO input is needed. The downconverter achieves a 40/39-dB image-rejection ratio of the first image and a 44/46-dB image-rejection ratio of the second image for 2.4/5.7-GHz modes, respectively.
Broadband CMOS Gilbert Down-Converter Utilizing a Low-Loss Step-Impedance Rat-Race Coupler
(2009)
Wei, Hung-Ju
;
Meng, Chinchun
;
Yu, Sheng-Wen
;
電信工程研究所
;
Institute of Communications Engineering
A Broadband Gilbert Down-Converter with step-impedance rat-race coupler is demonstrated using 0.13 mu m standard CMOS technology. The proposed method utilizes higher effective dielectric-constant, phase-inverter and step-impedance techniques simultaneously to make the rat-race coupler more compact (similar to 64% reduction) and phase-balanced over a wide operating bandwidth. The down-converter has NF of 16 dB and LO-to-RF isolation of better than 35 dB. The mixer core consumes 2.9 mA at V(dd)=1.8 V.
A high 2LO-to-RF isolation GaInP/GaAs HBT sub-harmonic Gilbert mixer using three-level topology
(2006)
Wu, Tzung-Han
;
Meng, Chinchun
;
Huang, Guo-Wei
;
電信工程研究所
;
Institute of Communications Engineering
A 5.2 GHz three-level sub-harmonic downconversion Gilbert mixer using GaInP/GaAs HBT (Heterojunction Bipolar Transistor) technology is demonstrated in this paper. The LO frequency is half of the RF frequency for the three-level sub-harmonic mixer architecture; therefore, the RF frequency is 5.2004 GHz and LO frequency is 2.6 GHz. The conversion gain is 14.5 dB, IP(1dB') is -18 dBm, IIP(2) is 13 dBm and the IIP(3) is -5 dBm when the LO power equals to -8 dBm. The 2LO-to-RF leakage is about -83 dBm. The RF input return loss is better than -18 dB from DC to 6GHz.
Broadband Gilbert micromixer with an LO Marchand balun and a TIA output buffer
(2006)
Tseng, Sheng-Che
;
Meng, Chinchun
;
Chang, Chia-Hung
;
Wu, Chih-Kai
;
Hung, Guo-Wei
A single-ended wideband downeonversion Gilbert micromixer is demonstrated in this paper using 0.35-um SiGe BiCMOS technology. Because of the wideband matching property of the micromixer, it can perform broad frequency translation. The TIA is utilized in the IF stage while a broadband Marchand balun is employed not only to generate differential LO signals but also to reserve the wideband operation of the mixer. This singleended wideband mixer has the conversion gain of 15 dB, IP(1dB) of 17 dBm, and IIP(3) of -6.5 dBm and works from 3.5 to 14.5 GHz. The input return loss is below -14 dB and the chip size is 1x1 mm(2).
60-GHz Dual-Conversion Down-/Up-Converters Using Schottky Diode in 0.18 mu m Foundry CMOS Technology
(2012-06-01)
Wei, Hung-Ju
;
Meng, Chinchun
;
Wang, Ta-Wei
;
Lo, Tai-Lin
;
Wang, Chia-Ling
Due to the benefits of Schottky diodes, 0.18-mu m CMOS technology is being promoted for millimeter wave applications. In this paper, 60-GHz dual-conversion down-/up-converters using Schottky diodes are realized by using 0.18-mu m foundry CMOS technology. A CoSi2-Si Schottky diode, fabricated on a lower doped N-well by blocking the threshold voltage adjustment implant, has a lower reverse leakage current and a better ideality factor. Thus, it is ideal for the 60-GHz sub-harmonic mixer design. Two new types of Schottky-diode mixers, a down-conversion sub-harmonic mixer with a dual-band lump-distributed phase-inverter rat-race coupler and an up-conversion sub-harmonic mixer with a trifilar transformer, are realized and employed at the high-frequency conversion stage of the dual-conversion architecture to achieve small size and broadband isolations. The silicon-based Schottky diode with a low turn-on voltage offers great advantage in LO pumping power, especially for an antiparallel diode pair structure. In our Schottky-diode sub-harmonic mixers, the required LO power is only 1 dBm. The dual-conversion down-converter achieves 5-dB conversion gain and 19 dB noise figure under V-dd = 2.5 V and I-dd = 22 mA, and the dual-conversion up-converter, with V-dd = 2.5 V and I-dd = 26 mA, attains greater than 40-dB sideband rejection and -1 dB conversion gain over the whole 60-GHz bandwidth.
Low-Power Sub-Harmonic Direct-Conversion Receiver With Tunable RF LNA and Wideband LO Generator at U-NII Bands
(2012-03-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
電機工程學系
;
Department of Electrical and Computer Engineering
A low-power tunable-band sub-harmonic direct-conversion receiver covering the whole Unlicensed National Information Infrastructure band is demonstrated using 0.18-mu m CMOS technology. The RF band is selected by tuning varactors at the loads of the two-stage low-noise amplifier, while a wideband octet-phase generator is applied at the local oscillator (LO) port. The band tuning of both an LC tank and a transformer and the design of an optimal transformer turn ratio are fully discussed in this paper. Vertical-NPN bipolar junction transistors in a standard CMOS process are used at the mixer switching core for excellent 1/f noise performance. As a result, the receiver achieves a 48/50 voltage gain and 4.5/4.8-dB noise figure with a 1/f noise corner of 70 kHz when the RF band is tuned to 5.2/5.8 GHz, respectively. The dc current consumption of the RF front-end (including the LO buffer) is 8.5 mA at a 1.8-V supply.
A 0.6-V 30 GHz CMOS Quadrature VCO Using Microwave 1:1:1 Trifilar Transformer
(2012-02-01)
Syu, Jin-Siang
;
Lu, Hsi-Liang
;
Meng, Chinchun
;
電機工程學系
;
Department of Electrical and Computer Engineering
A 30 GHz trifilar-transformer-coupled quadrature voltage-controlled oscillator (QVCO) is proposed in this letter using 0.13 mu m CMOS technology. The trifilar transformer provides dc decoupling as well as ac mutual coupling from drain, gate, and source nodes. The mutual coupling increases the overall quality factor while the gate/drain-to-source coupling provides quadrature coupling. The proposed 1:1:1 trifilar transformer realization has lower ohmic loss than the conventional trifilar transformer realization and is especially suitable for high-frequency applications. As a result, the proposed 30 GHz QVCO has a -195 dBc/Hz figure of merit (FOM) and a maximum 41.6 dB sideband rejection (SBR) at a 0.6 V supply.
2.4-GHz Low-Noise Direct-Conversion Receiver With Deep N-Well Vertical-NPN BJT Operating Near Cutoff Frequency
(2011-12-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
Wang, Chia-Ling
;
電機工程學系
;
Department of Electrical and Computer Engineering
A 2.4-GHz low-power low-noise direct-conversion receiver is demonstrated using parasitic vertical-NPN bipolar junction transistors (BJTs) in a standard 0.18-mu m CMOS process. The current switching operation of a Gilbert mixer with finite transistor cutoff frequency (f(T)) is thoroughly analyzed and discussed in this paper. When the mixer operates near or higher than the transistor f(T), the loss of the polyphase filter due to the capacitive loading of the mixer is a main issue. Thus, BJT devices with smaller base resistance and an inductive peaking technique with symmetric 3-D realization are employed in this paper to reduce local oscillator power by 4.5 dB. At 2.4 GHz, the demonstrated receiver has conversion gain of 51 dB and noise figure of 3.2 dB with 70-kHz 1/f noise corner, while the current consumption is 4.5 mA at a 1.8-V supply.

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