<link rel="stylesheet" href="styles.cf390c6bfbe7555f.css">

學術出版;;Publications

Permanent URI for this communityhdl:11536/1

收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

Browse

🏛️國立陽明交通大學機構典藏

Access type: Open accessAuthor: search.filters.author.Su, Pin

Search Results

Now showing 1 - 10 of 57
  • Thumbnail Image
    Item type:Item,
    New Findings on the Drain-Induced Barrier Lowering Characteristics for Tri-Gate Germanium-on-Insulator p-MOSFETs
    (2015-11-01)
    Wu, Shu-Hua
    ;
    Yu, Chang-Hung
    ;
    Su, Pin
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This paper investigates the intrinsic drain-induced barrier lowering (DIBL) characteristics for tri-gate germanium-on-insulator (GeOI) p-MOSFETs through theoretical calculation by analytical solution of 3-D Poisson's equation corroborated with TCAD numerical simulation. It is found that, relative to the silicon-on-insulator counterpart, there exists a build-in negative substrate bias in the GeOI PFET. This built-in substrate bias, stemming mainly from the large discrepancy in bandgap between Ge and Si, pulls the carriers toward the channel/BOX interface and thus degrades the DIBL of the GeOI PFET beyond what permittivity predicts. This new mechanism has to be considered when designing or benchmarking tri-gate GeOI p-MOSFETs.
  • Thumbnail Image
    Item type:Item,
    Evaluation of Monolithic 3-D Logic Circuits and 6T SRAMs With InGaAs-n/Ge-p Ultra-Thin-Body MOSFETs
    (2016-03-01)
    Yu, Kuan-Chin
    ;
    Fan, Ming-Long
    ;
    Su, Pin
    ;
    Chuang, Ching-Te
    ;
    電子工程學系及電子研究所
    This paper evaluates monolithic 3-D logic circuits and 6T SRAMs composed of InGaAs-n/Ge-p ultra-thin-body MOSFETs while considering interlayer coupling through TCAD mixed-mode model. This paper indicates that monolithic 3-D InGaAs/Ge logic circuits provide equal leakage and better delay performance compared with planar 2-D structure through optimized 3-D layout. The monolithic 3-D InGaAs/Ge 6T SRAMs can simultaneously improve the cell stability and performance through optimized 3-D layout. We suggest two 3-D SRAM layout designs for high performance and low power applications, respectively. Moreover, with optimized 3-D layout designs, InGaAs/Ge logic circuits exhibit larger delay improvement, and the 6T SRAMs exhibit larger read access time and time-to-write improvement compared with Si counterparts.
  • Thumbnail Image
    Item type:Item,
    Theoretical Investigation of DIBL Characteristics for Scaled Tri-Gate InGaAs-OI n-MOSFETs Including Sensitivity to Process Variations
    (2017-01-01)
    Wu, Shu-Hua
    ;
    Yu, Chien-Lin
    ;
    Yu, Chang-Hung
    ;
    Su, Pin
    ;
    電子工程學系及電子研究所
    This paper investigates the intrinsic drain-induced barrier lowering (DIBL) characteristics of highly-scaled tri-gate n-MOSFETs with InGaAs channel based on ITRS 2021 technology node through numerical simulation corroborated with theoretical calculation. This paper indicates that, when studying short-channel effects in III-V FETs, one has to account for quantum-confinement, or else predictions will be pessimistic. Due to 2-D quantum-confinement, the DIBL of the InGaAs tri-gate devices can be significantly suppressed and be comparable to the Si counterpart. Besides, for highly-scaled InGaAs tri-gate NFETs, the impact of buried-oxide thickness on DIBL becomes minor, and the DIBL sensitivity to the fin-width and gate-length variations can also be suppressed by the quantum-confinement effect. This paper may provide insights for tri-gate device design using III-V high-mobility channel materials.
  • Thumbnail Image
    Item type:Item,
    Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits
    (2014-12-01)
    Chen, Yin-Nien
    ;
    Fan, Ming-Long
    ;
    Hu, Vita Pi-Ho
    ;
    Su, Pin
    ;
    Chuang, Ching-Te
    In this work, we propose a mixed TFET-MOSFET 8T SRAM cell comprising MOSFET cross-coupled inverters, dedicated TFET read stack and TFET write access transistors for ultra-low voltage operation. Exploiting both the merits of TFET and MOSFET devices, the proposed SRAM cell provides significant improvement in SRAM stability, V-min and performance. The stability and performance of the proposed cell are evaluated and compared with the conventional MOSFET 8T cell and pure TFET 8T cell using mixed-mode TCAD simulations based on published design rules for 22 nm technology node. Besides, the impacts of the device design of the proposed SRAM cell on the stability are also investigated. Various write-assist techniques to enhance the write-ability across V-DD = 0.2 to 0.7 V for these SRAM cells are comparatively assessed. The results indicate that the proposed mixed TFET-MOSFET cell topology is viable for ultra-low voltage operation while MOSFET cell provides better stability and performance for high voltage operation.
  • Thumbnail Image
    Item type:Item,
    Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices
    (2014-12-01)
    Chen, Yin-Nien
    ;
    Fan, Ming-Long
    ;
    Hu, Vita Pi-Ho
    ;
    Su, Pin
    ;
    Chuang, Ching-Te
    This paper investigates the feasibility of sub-0.2 V high-speed low-power circuits with hetero-channel MOSFET and emerging Tunneling FET (TFET) devices. First, the device designs and characteristics of hetero-channel MOSFET and TFET devices are discussed and compared. Due to the significant leakage current of ultra-low V-T hetero-channel MOSFET devices, assist-circuits are required for hetero-channel MOSFET-based circuits to operate at 0.2 V. Second, the delay, dynamic energy and the Standby power of hetero-channel TFET-based and MOSFET-based logic circuits including Inverter, NAND, BUS Driver, and Latch are analyzed and evaluated. The results indicate that hetero-channel TFET-based circuits with Dual Oxide (DOX) device design to reduce the Miller capacitance provide the potential to achieve high-speed low-power operation at V-DD = 0.2 V, while the use of assist-circuits in MOSFET-based design improves the delay and dynamic energy at the expense of increased device count, circuit area, and large Standby and sleep-mode leakage power. Finally, the impacts of temperature and process variations on TFET-based and MOSFET-based logic circuits are discussed.
  • Thumbnail Image
    Item type:Item,
    Temperature-Dependent RF Small-Signal and Noise Characteristics of SOI Dynamic Threshold Voltage MOSFETs
    (2010-09-01)
    Wang, Sheng-Chun
    ;
    Su, Pin
    ;
    Chen, Kun-Ming
    ;
    Liao, Kuo-Hsiang
    ;
    Chen, Bo-Yuan
    In this paper, temperature-dependent RF small-signal and noise characteristics of silicon-on-insulator (SOI) dynamic threshold voltage (DT) MOSFETs are experimentally examined. In the low-voltage regime, both the cutoff and maximum oscillation frequencies (f(t) and f(max)) tend to increase with temperature. In addition, the inherent body-related parasitics and the series resistance have much more impact on f(max) than f(t). Besides, we found that the noise stemmed from the body resistance (R(b)) would contribute to the output noise current, and degrade the minimum noise figure (NF(min)). Our study may provide insights for RF circuit design using advanced SOI DT MOSFETs.
  • Thumbnail Image
    Item type:Item,
    Radio-Frequency Small-Signal and Noise Modeling for Silicon-on-Insulator Dynamic Threshold Voltage Metal-Oxide-Semiconductor Field-Effect Transistors
    (2009-04-01)
    Wang, Sheng-Chun
    ;
    Su, Pin
    ;
    Chen, Kun-Ming
    ;
    Huang, Sheng-Yi
    ;
    Hung, Cheng-Chou
    This paper presents small-signal and noise modeling for radio-frequency (RF) silicon-on-insulator (SOI) dynamic threshold voltage (DT) metal-oxide-semiconductor field-effect transistors (MOSFETs). The inherent body parasitics, such as source- and drain-side junction capacitances, and access body resistance have been incorporated in this model. In addition, the analytical equations useful for parameter extractions are derived. The modeling results show good agreements with the measured data both in RF small-signal and noise aspects up to 12 GHz. Besides, we have made comparisons of important model parameters for DT and standard MOSFETs. The extracted parameters show reasonable trend with respect to applying voltages and channel lengths, which reveals the accuracy of the extraction results using our proposed method. (C) 2009 The Japan Society of Applied Physics
  • Thumbnail Image
    Item type:Item,
    Impact of Surface Orientation on the Sensitivity of FinFETs to Process Variations-An Assessment Based on the Analytical Solution of the Schrodinger Equation
    (2010-12-01)
    Wu, Yu-Sheng
    ;
    Su, Pin
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This paper investigates the impact of surface orientation on V(th) sensitivity to process variations for Si and Ge fin-shaped field-effect transistors (FinFETs) using an analytical solution of the Schrodinger equation. Our theoretical model considers the parabolic potential well due to short-channel effects and, therefore, can be used to assess the quantum-confinement effect in short-channel FinFETs. Our study indicates that, for ultrascaled FinFETs, the importance of channel thickness (t(ch)) variations increases due to the quantum-confinement effect. The Si-(100) and Ge-(111) surfaces show lower V(th) sensitivity to the t(ch) variation as compared with other orientations. On the contrary, the quantum-confinement effect reduces the V(th) sensitivity to the L(eff) variation, and Si-(111) and Ge-(100) surfaces show lower V(th) sensitivity as compared with other orientations. Our study may provide insights for device design and circuit optimization using advanced FinFET technologies.
  • Thumbnail Image
    Item type:Item,
    Impact of Quantum Confinement on Short-Channel Effects for Ultrathin-Body Germanium-on-Insulator MOSFETs
    (2011-01-01)
    Wu, Yu-Sheng
    ;
    Hsieh, Hsin-Yuan
    ;
    Hu, Vita Pi-Ho
    ;
    Su, Pin
    ;
    電子工程學系及電子研究所
    This letter investigates the impact of quantum confinement (QC) on the short-channel effect (SCE) of ultrathin-body (UTB) and thin-buried-oxide germanium-on-insulator (GeOI) MOSFETs using an analytical solution of Schrodinger equation verified with TCAD simulation. Our study indicates that, although the QC effect increases the threshold voltage (V(th)) roll-off when the channel thickness (T(ch)) is larger than a critical value (T(ch,crit)), it may decrease the V(th) roll-off of GeOI MOSFETs when the T(ch) is smaller than T(ch,crit). Since Ge and Si channels exhibit different degrees of confinement and T(ch,crit), the impact of QC must be considered when one-to-one comparisons between UTB GeOI and Si-on-insulator MOSFETs regarding the SCE are made.
  • Thumbnail Image
    Item type:Item,
    Experimental Investigation of Surface-Roughness-Limited Mobility in Uniaxial Strained pMOSFETs
    (2011-02-01)
    Chen, William P. N.
    ;
    Kuo, Jack J. Y.
    ;
    Su, Pin
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This letter provides an experimental assessment of surface-roughness-scattering-limited mobility (mu(SR)) under process-induced uniaxial strain and compares the strain sensitivity between mu(SR) and phonon-scattering-limited mobility (mu(PH)). By an accurate split C-V mobility extraction method, the mu(SR) of short-channel pMOSFETs was extracted at an ultralow temperature to suppress the phonon scattering mechanism. Our result indicates that mu(SR) has stronger stress sensitivity than mu(PH). Furthermore, the surface roughness mobility enhancement tends to increase as the vertical electric field increases. Our experimental findings confirm the previously reported results based on simulations.