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A 2.4-GHz Low-Flicker-Noise CMOS Sub-Harmonic Receiver
(2013-02-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
Wang, Chia-Ling
;
電機工程學系
;
Department of Electrical and Computer Engineering
A 2.4-GHz low-noise sub-harmonic direct-conversion receiver (SH-DCR) is demonstrated using standard 0.18-mu m CMOS technology. Deep-n-well vertical-NPN (V-NPN) bipolar junction transistors (BJTs) are employed to solve the flicker noise problem in CMOS process. Design optimization of a power-constrained noise-impedance-matched low-noise amplifier (LNA) with the effect of lossy on-chip inductors is fully discussed in this paper. A multi-stage octet-phase polyphase filter is analyzed in detail and implemented to generate well balanced octet-phase LO signals. As a result, the demonstrated receiver achieves 51-dB voltage gain and 3-dB noise figure with flicker noise corner less than 30 kHz when RF = 2.4 GHz. The I/Q amplitude/phase mismatch is below +/-0.2 dB/+/-1 degrees, respectively, covering from 2.35 to 2.6 GHz. The dc current consumption is 5 mA at a 1.8-V supply.
2.4/5.7-GHz Dual-Band Dual-Conversion Architecture With Correlated LO Signal Generators
(2009)
Syu, Jin-Siang
;
Meng, Chinchun
;
Yu, Sheng-Wen
;
Wu, Tzung-Han
;
Huang, Guo-Wei
A 2.4/5.7-GHz dual-band dual-conversion downconverter is demonstrated using 0.35-mu m SiGe hetero-junction bipolar transistor (HBT) technology. This downconverter employs a complex dual-conversion system and a complex filter to reject the first and second image signals, respectively. The LO(1) frequency is 2.5 times the LO(2) frequency and is generated by a divide-by-two divider, a frequency doubler and a single-sideband up-converter. As a result, the correlated LO signals maintain excellent image-rejection performance of the dual-conversion system while only one LO input is needed. The downconverter achieves a 40/39-dB image-rejection ratio of the first image and a 44/46-dB image-rejection ratio of the second image for 2.4/5.7-GHz modes, respectively.
Low-Power Sub-Harmonic Direct-Conversion Receiver With Tunable RF LNA and Wideband LO Generator at U-NII Bands
(2012-03-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
電機工程學系
;
Department of Electrical and Computer Engineering
A low-power tunable-band sub-harmonic direct-conversion receiver covering the whole Unlicensed National Information Infrastructure band is demonstrated using 0.18-mu m CMOS technology. The RF band is selected by tuning varactors at the loads of the two-stage low-noise amplifier, while a wideband octet-phase generator is applied at the local oscillator (LO) port. The band tuning of both an LC tank and a transformer and the design of an optimal transformer turn ratio are fully discussed in this paper. Vertical-NPN bipolar junction transistors in a standard CMOS process are used at the mixer switching core for excellent 1/f noise performance. As a result, the receiver achieves a 48/50 voltage gain and 4.5/4.8-dB noise figure with a 1/f noise corner of 70 kHz when the RF band is tuned to 5.2/5.8 GHz, respectively. The dc current consumption of the RF front-end (including the LO buffer) is 8.5 mA at a 1.8-V supply.
A 0.6-V 30 GHz CMOS Quadrature VCO Using Microwave 1:1:1 Trifilar Transformer
(2012-02-01)
Syu, Jin-Siang
;
Lu, Hsi-Liang
;
Meng, Chinchun
;
電機工程學系
;
Department of Electrical and Computer Engineering
A 30 GHz trifilar-transformer-coupled quadrature voltage-controlled oscillator (QVCO) is proposed in this letter using 0.13 mu m CMOS technology. The trifilar transformer provides dc decoupling as well as ac mutual coupling from drain, gate, and source nodes. The mutual coupling increases the overall quality factor while the gate/drain-to-source coupling provides quadrature coupling. The proposed 1:1:1 trifilar transformer realization has lower ohmic loss than the conventional trifilar transformer realization and is especially suitable for high-frequency applications. As a result, the proposed 30 GHz QVCO has a -195 dBc/Hz figure of merit (FOM) and a maximum 41.6 dB sideband rejection (SBR) at a 0.6 V supply.
2.4-GHz Low-Noise Direct-Conversion Receiver With Deep N-Well Vertical-NPN BJT Operating Near Cutoff Frequency
(2011-12-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
Wang, Chia-Ling
;
電機工程學系
;
Department of Electrical and Computer Engineering
A 2.4-GHz low-power low-noise direct-conversion receiver is demonstrated using parasitic vertical-NPN bipolar junction transistors (BJTs) in a standard 0.18-mu m CMOS process. The current switching operation of a Gilbert mixer with finite transistor cutoff frequency (f(T)) is thoroughly analyzed and discussed in this paper. When the mixer operates near or higher than the transistor f(T), the loss of the polyphase filter due to the capacitive loading of the mixer is a main issue. Thus, BJT devices with smaller base resistance and an inductive peaking technique with symmetric 3-D realization are employed in this paper to reduce local oscillator power by 4.5 dB. At 2.4 GHz, the demonstrated receiver has conversion gain of 51 dB and noise figure of 3.2 dB with 70-kHz 1/f noise corner, while the current consumption is 4.5 mA at a 1.8-V supply.
2.4/5.7 GHz dual-band high linearity gilbert upconverter utilizing bias-offset TCA and LC current combiner
(2007-12-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
電信工程研究所
;
Institute of Communications Engineering
A 2.4/5.7 GHz dual-band Gilbert upconversion mixer is demonstrated using 0.35 mu m SiGe BiCMOS technology. A bias-offset cross-coupled transconductance amplifier (TCA) is employed in the intermediate frequency port for the linearity improvement. The dual-band LC current combiner and the output shunt-shunt feedback buffer amplifier are in the radio frequency (RF) port. The mechanisms of the high linearity upconverter and, the design flow of the dual-band LC current combiner are established in this letter. The dual-band upconverter has conversion gain of 1.5/-0.2 dB, OP1dB of -10.5/-9 dBm, and OIP3 of 12/13 dBm for IF=100 MHz, RF= 2.4/5.7 GHz, respectively.
5.7 GHz Gilbert I/Q downconverter integrated with a passive LO quadrature generator and an RF Marchand balun
(2008-02-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
Yen, Ying-Chieh
;
電信工程研究所
;
Institute of Communications Engineering
A 5.7 GHz I/Q downconversion mixer is demonstrated in this letter using 0.35 mu m SiGe BiCMOS technology. A quarter-wavelength coupled line and two center-tapped transformers are utilized to generate differential quadrature LO signals. A miniaturized Marchand balun is placed before the common-base-configured RF input stage of each I/Q Gilbert mixer to generate balanced RF signals. All the reactive passive elements are placed directly on the standard silicon substrate. The 5.7 GHz I/Q downconverter achieves 7 dB conversion gain, -26 dBm IP1dB, and -18 dBm IIP3 at the power consumption of 3.875 mW and 2.5 V supply voltage.
Comparison of wideband Gilbert micromixers using SiGe HBT and GaInP/GaAs HBT technologies
(2008-09-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
Wu, Chih-Kai
;
Huang, Guo-Wei
;
電信工程研究所
Wideband downconversion mixers are demonstrated by using both 0.35-mu m SiGe heterojunction bipolar transistor (HBT) and 2-mu m GaInP/GaAs HBT technologies. A micromixer topology is implemented in the RF port while a differential type shunt-shunt feedback amplifier and a differential-to-single CE-CC output buffer are used in the IF stage. The frequency response analysis and systematic measurement approach for a wideband Gilbert mixer are proposed in this article for each individual stage of local frequency (LO), radio frequency (RF), and intermediate frequency (IF). The differential LO signals are generated by several off-chip 180 degrees hybrids to cover more than 8:1 bandwidth. The SiGe HBT Micromixer achieves the conversion gain of 6 dB, IP(IdB) of -17.5 dBm, and IIP(3) of - 7 dBm with the 3.3-V supply voltage and the power consumption of 37.5 mW. On the other hand, the GaInP/GaAs HBT Micromixer achieves the conversion gain of 25 dB, IP(IdB) of -25 dBm, and IIP(3) of - 15 dBm with the 5-V supply voltage and the power consumption of 50 mW. (c) 2008 Wiley Periodicals, Inc.
Characteristics of GaAs transformers for RFIC applications
(2008-11-01)
Meng, Chinchun
;
Teng, Ya-Hui
;
Syu, Jin-Siang
;
Lin, Yi-Chen
;
Jhong, Jhin-Ci
In this article, stacked transformers, coupling stacked transformers, interleave transformers, and symmetrical transformers on GaAs substrate are systematically studied. Two kinds of stacked transformer are under study. One has the symmetrical electric property while the other one has a better quality factor for the primary port. The stack transformers have achieved the highest coupling coefficient (similar to 0.9) at the cost of lower self-resonance frequency. The interleave transformers have the identical electrical properties for the primary and the secondary ports. However, the layout is incompatible with the differential operation. Oil the other hand, the symmetrical transformer is compatible with the differential operation (aid call have the center-tapped biasing option. The data established here provides a useful design library for the GaAs RFIC. (C) 2008 Wiley Periodicals, Inc.
2.4/5.7-GHz CMOS Dual-Band Low-IF Architecture Using Weaver-Hartley Image-Rejection Techniques
(2009-03-01)
Meng, Chin-Chun
;
Wu, Tzung-Han
;
Syu, Jin-Siang
;
Yu, Sheng-Wen
;
Tsung, Kuan-Chang
A 2.4/5.7-GHz dual-band Weaver-Hartley architecture, using 0.18-mu m CMOS technology, is demonstrated in this paper. The 2.4-GHz signal is set to be the image signal when the desired signal is at 5.7 GHz, and vice versa. Since the Weaver and Hartley systems are combined into this architecture, the demonstrated architecture rejects not only the first image signal, but also the secondary image signal. The image-rejection ratios of the first image signal and the secondary image signal are better than 40 and 46 dB, respectively. In this paper, a diagrammatic explanation is employed to obtain the image-rejection mechanisms of the Weaver-Hartley architecture.

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