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Access type: Open accessSubject: search.filters.subject.CMOS technology

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    A 2-V low-power CMOS direct-conversion quadrature modulator with integrated quadrature voltage-controlled oscillator and RF amplifier for GHz RF transmitter applications
    (2002-02-01)
    Wu, CY
    ;
    Kao, HS
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A compact low-voltage low-power CMOS direct-conversion quadrature modulator with integrated quadrature voltage-controlled oscillator (VCO) and radio frequency (RF) amplifier for wireless transmitter applications is proposed and analyzed. By applying both baseband input signals with quadrature phases and quadrature local oscillator (LO) signals to a set of combiners, the quadrature modulation functions can be implemented. The low-power operation is enabled by the current reuse technique used among quadrature modulator, quadrature VCO, and RF amplifier. Because only two transistors and one resistor are cascoded in the critical path of the proposed quadrature modulator between power supply and ground, the supply voltage can be as low as 1.5 V. The proposed circuit structure is used to design a quadrature modulator chip for 1.9-GHz digital enhanced cordless telecommunications (DECT) transmitter applications. The experimental chip is fabricated by using 0.35-mum n-well double-poly-triple-metal (DPTM) CMOS technology. The power dissipation is only 18 mW under 2-V power supply voltage. The on-chip quadrature VCO can provide highly accurate quadrature signals without any phase tuning or trimming. The frequency tuning range of the quadrature VCO is 280 MHz from 1.89 to 2.17 GHz at 2-V supply voltage. Due to small mismatch among quadrature signal paths, the measured image ratio is below -42 dBc under 2-V supply voltage when the desired upper side-band (USB) is set at 2 GHz and -51 dBc under 3-V supply voltage when the desired USB at 1.94 GHz. At 2-V supply voltage, the measured LO leakage is -48 dBc. Moreover, the measured second-order intermodulation and third-order intermodulation are less than -46 dBc.
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    New current-mode wave-pipelined architectures for high-speed analog-to-digital converters
    (2004-01-01)
    Wu, CY
    ;
    Liow, YY
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    In this paper, two new architectures for high-speed CMOS wave-pipelined current-mode A/D converters (WP-IADCs) are proposed and analyzed. In the new WP-IADC architectures, the wave-pipelined theory is applied to both pipeline structures, called full WP-IADC (FWP-IADC) and indirect transfer WP-IADC (ITWP-IADC). In the FWP-IADC, each stage uses the full current-mode wave-pipelined structure without switched-current cell circuits. In the ITWP-IADC, the switched-current cells are incorporated into the wave-pipelined stages which are divided into several sections with controlled clocks. Therefore, the proposed ITWP-IADC performs optimally in terms of speed and accuracy in the WP-IADCs. Generally, the proposed WP-IADCs have the advantages of high speed, high input frequency, high efficiency of timing usage, high clock-period flexibility in switched-current cells for precision enhancement, and reduced number of switched-current cells in the overall data path for linearity improvement. According to the theoretical analysis on the proposed WP-IADC structures, the minimum sampling clock period is proportional to the intrinsic delay of the current mirror and the increased rise/fall time in each wave-pipelined stage. The HSPICE simulation results reveal that, under Nyquist rate sampling in 8-b resolution, a sampling rate of 20 and 54 MHz can be achieved for FWP-IADC and two-section ITWP-LADC, respectively. If four wave-pipelined sections are used, the ITWP-IADC can be operated at 166 MHz at an input frequency of 8 MHz. To experimentally verify the correct function of the proposed WP-IADC structures, the proposed new architecture of the FWP-IADC is implemented by using 0.35-mum CMOS technology. The measurement results successfully demonstrate the feasibility of wave-pipelined IADC architectures in applications of high-speed ADCs.
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    A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator
    (2004-03-01)
    Wu, CY
    ;
    Chou, CY
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A 5-GHz CMOS double-quadrature front-end receiver for wireless LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals. Implemented in 0.18 mum CMOS technology, the receiver chip can achieve 50.6-dB image rejection with power dissipation of 22.4 mW at 1.8-V voltage supply.
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    The design of wideband and low-power CMOS active polyphase filter and its application in RF double-quadrature receivers
    (2005-05-01)
    Chou, CY
    ;
    Wu, CY
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    In this work, a new technique to implement the transfer function of polyphase filter with CMOS active components is proposed and analyzed. In the proposed polyphase filter structure, the currents mirrored from capacitors and the transistors in a single-stage are used to realize high-pass and low-pass functions, respectively. The multistage structure expands the frequency bandwidth to more than 20 MHz. Furthermore, a constant-gm bias circuit is employed to decrease the sensitivity of image rejection to temperature and process variations. HSPICE simulations are performed to confirm the performance. With the current-mode operation, the low-voltage version of proposed active polyphase filters was designed. It can be operated at IN power supply with similar performance but with only 50% of the power dissipation of the normal-voltage version. The proposed four-stage polyphase filter is fabricated in 0.25-μ m CMOS 1P5M technology. The measured image rejection ratio is higher than -48 dB at frequencies of 6.1 MHz &SIM; 30 MHz. The measured voltage gain is 6.6 dB at 20 MHz and IIP3 is 8 dBm. The power dissipation is 11 mW at a supplied voltage of 2.5 V and the active chip area is 1162 x 813 μ m(2).
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    The design of a 3-V 900-MHz CMOS bandpass amplifier
    (1997-02-01)
    Wu, CY
    ;
    Hsiao, SY
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A new bandpass amplifier which performs both functions of low-noise amplifier (LNA) and bandpass filter (BPF) is proposed for the application of 900-MHz RF front-end in wireless receivers, In the proposed amplifier, the positive-feedback Q-enhancement technique is used to overcome the low-gain low-Q characteristics of the CMOS tuned amplifier, The Miller capacitance tuning scheme is used to compensate for the process variations of center frequency, Using the high-Q bandpass amplifier in the receivers, the conventional bulky off-chip filter is not required, An experimental chip fabricated by 0.8-mu m N-well double-poly-double-metal CMOS technology occupies 2.6 x 2.0 mm(2) chip area, Under a 3 V supply voltage, the measured quality factor is tunable between 2.2 and 44. When the quality factor is tuned at Q = 30, the measured center frequency of the amplifier is tunable between 869-893 MHz with power gain 17 dB, noise figure 6.0 dB, output 1 dB compression point at -30 dBm, third-order input intercept point at -14 dBm, and power dissipation 78 mW.