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Gate-Stack Engineering for Self-Organized Ge-dot/SiO2/SiGe-Shell MOS Capacitors
(2016-02-11)
Lai, Wei-Ting
;
Yang, Kuo-Ching
;
Liao, Po-Hsiang
;
George, Tom
;
Li, Pei-Wen
We report the first-of-its-kind, self-organized gate-stack heterostructure of Ge-dot/SiO2/SiGe-shell on Si fabricated in a single step through the selective oxidation of a SiGe-nanopatterned pillar over a Si3N4 buffer layer on a Si substrate. Process-controlled tunability of the Ge-dot size (7.5-90 nm), the SiO2 thickness (3-4 nm), and the SiGe-shell thickness (2-15 nm) have been demonstrated, enabling a practically achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices. Detailed morphologies, structural, and electrical interfacial properties of the SiO2/Ge-dot and SiO2/SiGe interfaces were assessed using transmission electron microscopy, energy dispersive X-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Notably, NiGe/SiO2/SiGe and Al/SiO2/Ge-dot/SiO2/SiGe MOS capacitors exhibit low interface trap densities of as low as 3-5 x 10(11) cm(-2) eV(-1) and fixed charge densities of 1-5 x 10(11) cm(-2), suggesting good-quality SiO2/SiGe-shell and SiO2/Ge-dot interfaces. In addition, the advantage of having single-crystalline Si1-xGex shell (x > 0.5) in a compressive stress state in our self-aligned gate-stack heterostructure has great promise for possible SiGe (or Ge) MOS nanoelectronic and nanophotonic applications.
Direct oxidation of Si1-xGex layers using Vacuum-Ultra-Violet light radiation in oxygen
(1998-02-01)
Chen, LP
;
Chan, YC
;
Chang, SJ
;
Huang, GW
;
Chang, CY
Oxidation of Si1-xGex films has been carried out by direct photo chemical Vapor deposition (direct photo-CVD) directly with activated O-2 induced by Vacuum-Ultra-Violet (VUV) light radiation, The Auger electron spectroscopy profiles show that no Ge-pileup layer at the oxide/Si1-xGex interface is observed after VUV-induced Si1-xGex oxidation process. The X-ray photoelectron spectroscopy analysis of the samples reveals that Si and Ge are oxidized simultaneously in oxidation process and a mixed oxide layer consisting both SiO2 and GeO2 is formed, This might be the reason that Cc pileup effect is eliminated in this study.
Nanogrids and Beehive-Like Nanostructures Formed by Plasma Etching the Self-Organized SiGe Islands
(2010-09-01)
Chang, Yuan-Ming
;
Jian, Sheng-Rui
;
Juang, Jenh-Yih
;
電子物理學系
;
Department of Electrophysics
A lithography-free method for fabricating the nanogrids and quasi-beehive nanostructures on Si substrates is developed. It combines sequential treatments of thermal annealing with reactive ion etching (RIE) on SiGe thin films grown on (100)-Si substrates. The SiGe thin films deposited by ultrahigh vacuum chemical vapor deposition form self-assembled nanoislands via the strain-induced surface roughening (Asaro-Tiller-Grinfeld instability) during thermal annealing, which, in turn, serve as patterned sacrifice regions for subsequent RIE process carried out for fabricating nanogrids and beehive-like nanostructures on Si substrates. The scanning electron microscopy and atomic force microscopy observations confirmed that the resultant pattern of the obtained structures can be manipulated by tuning the treatment conditions, suggesting an interesting alternative route of producing self-organized nanostructures.
High temperature formed SiGeP-MOSFET's with good device characteristics
(2000-07-01)
Wu, YH
;
Chin, A
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We have used a simple process to fabricate Si0.3Ge0.7/Si p-MOSFET's. The Si0.3Ge0.7 is formed using deposited Ge followed by 950 degrees C rapid thermal annealing and solid phase epitaxy that is process compatible with existing VLSI. Hole mobility of 250 cm(2)/Vs is obtained from Si0.3Ge0.7 p-MOSFET that is similar to two times higher than Si control devices and results in a consequent substantially higher current drive. The 228 Angstrom Si0.3Ge0.7 thermal oxide grown at 1000 degrees C has a high breakdown field of 15 MV/cm, low interface trap density (D-it) of 1.5 x 10(11) eV(-1) cm(-2), and low oxide charge of 7.2 x 10(10) cm(-2). The source-drain junction leakage after implantation and 950 degrees C RTA is also comparable with Si counterpart.
Formation of Ni germano-silicide on single crystalline Si0.3Ge0.7/Si
(2002-08-01)
Lin, CY
;
Chen, WJ
;
Lai, CH
;
Chin, A
;
Liu, J
We have studied the Ni and Co germano-silicide on Si0.3Ge0.7/Si. The Ni germano-silicide shows a low sheet resistance of 4-6 Omega/square on both P+N and N+P junctions, which is much smaller than Co germano-silicide. In addition, small junction leakage currents of 3 x 10(-8) A/cm(2) and 2 x 10(-7) A/cm(2) are obtained for Ni germano-silicide on P+ N and N+ P junctions, respectively. The good germano-silicide integrity is due to the relatively uniform thickness as observed by cross-sectional TEM.
La2O3/Si0.3Ge0.7 p-MOSFETs with high hole mobility and good device characteristics
(2002-12-01)
Huang, CH
;
Chen, SB
;
Chin, A
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We have studied the high-k La2O3 p-MOSFETs on Si0.3Ge0.7 substrate. Nearly identical gate oxide current, capacitance density, and time-dependent dielectric breakdown (TDDB) re obtained for La2O3/Si and La2O3/Si0.3Ge0.7 devices that indicate the excellent Si0.3Ge0.7 quality without any side effect. The measured hole mobility in nitrided La2O3/Si p-MOSFETs is 31 cm(2)/V-s and comparable with published data in nitrided HfO2/Si p-MOSFETs. In sharp contrast, a higher mobility of 55 cm(2)/V-s is measured in La2O3/Si0.3Ge0.7 p-MOSFET, which is improved by 1.8 times as compared with La2O3/Si control devices. The high mobility in Si0.3Ge0.7 p-MOSFET gives another step for integrating high-k gate dielectrics into VLSI process.
A novel SiGe raised source/drain polycrystalline silicon thin-film transistor with improved on-current and larger breakdown voltage
(2003-03-01)
Peng, DZ
;
Chang, TC
;
Liu, CF
;
Yeh, PH
;
Liu, PT
A novel poly-Si thin-film transistor with a self-aligned SiGe raised source/drain (SiGe-RSD TFT) has been proposed and fabricated. The SiGe-RSD regions were grown selectively by the ultra-high vacuum chemical vapor deposition (UHVCVD) process designed by us at 550degreesC. The resultant transistor structure features an ultra-thin active channel region (20 nm) and a self-aligned thick source/drain region (120 nm), and is ideally suited for optimum performance. Significant improvements in electrical characteristics, such as higher turn-on current, lower leakage current and higher drain breakdown voltage have been observed in the SiGe RSD TFT, compared to its conventional TFT counterpart. Moreover, the process is simple and no additional masks are necessary, which is consistent with conventional fabrication processes.
Growth of high-quality Ge epitaxial layers on Si(100)
(2003-05-15)
Luo, GL
;
Yang, TH
;
Chang, EY
;
Chang, CY
;
Chao, KA
A method of growing high-quality epitaxial Ge layers on a Si(100) substrate is reported. In this method, a 0.8 mum Si0.1Ge0.9 layer was first grown. Due to the large lattice mismatch between this layer and the Si substrate, many dislocations form near the interface and in the lower part of the Si0.1Ge0.9 layer. A 0.8 mum Si0.05Ge0.95 layer and a 1.0 mum top Ge layer were subsequently grown on the Si0.1Ge0.9 layer. The formed interfaces of Si0.05Ge0.95/Si0.1Ge0.9 and Ge/Si0.05Ge0.95 can bend and terminate the upward-propagated dislocations very effectively. The in situ annealing process was also performed for each individual layer. Experimental results show that the dislocation density in the top Ge layer can be greatly reduced, and the surface is very smooth, while the total thickness of the structure is only 2.6 mum.
Study of nickel silicide contact on Si/Si1-xGex
(2003-09-01)
Yang, TH
;
Luo, GL
;
Chang, EY
;
Yang, TY
;
Tseng, HC
The properties of nickel silicide formed by depositing nickel on Si/P+ - Si1-xGex layer are compared with that of nickel germanosilicide on P+ - Si1-xGex layer formed by depositing Ni directly on P+ - Si1-xGex layer without silicon consuming layer. After thermal annealing, nickel silicide on Si/P+ S Si1-xGex layer shows lower sheet resistance and specific contact resistivity than that of nickel germanosilicide on P+ - Si1-xGex layer. In addition, small junction leakage current is also observed for nickel silicide on Si/P+ - Si1-xGex/N - Si diode. In summary, witha Si consuming layer on top of the Si1-xGex, the nickel silicide contact formed demonstrated improved electrical and materials characteristics as compared with the nickel germanosilicide contact which was formed directly on Si1-xGex layer.
Light emission near 1.3 mu m using ITO-Al2O3-Si0.3Ge0.7-Si tunnel diodes
(2004-01-01)
Lin, CY
;
Chin, A
;
Hou, YT
;
Li, MF
;
McAlister, SP
We have fabricated Sn:In2O3 (ITO)-Al2O3 dielectric on Si1-xGex-Si metal-oxide-semiconductor tunnel diodes which emit light at around 1.3 mum, for x = 0.7. The emitted photon energy is smaller than the bandgap energy of Si, thus, avoiding strong light absorption by the Si substrate. The optical device structure is compatible with that of a metal-oxide-semiconductor field-effect transistor, since a conventional doped poly-Si gate electrode will be transparent to the emitted light. Increasing the Ge composition from 0.3 to 0.4 only slightly decreases the light-emitting efficiency.

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