學術出版;;Publications

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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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Cleaning policies in mobile computers using flash memory
(1999-11-01)
Chiang, ML
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Chang, RC
;
資訊工程學系
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Department of Computer Science
Flash memory is small, lightweight, shock-resistant, nonvolatile, and consumes little power. Flash memory therefore shows promise for use in storage devices for consumer electronics, mobile computers and embedded systems. However, flash memory cannot be overwritten unless erased in advance. Erase operations are slow that usually decrease system performance, and consume power. The number of erase cycles is also limited. For power conservation, better system performance, and longer flash memory lifetime, system support for erasure management is necessary. In this paper, we use the non-update-in-place scheme to implement a flash memory server and propose a new cleaning policy to reduce the number of erase operations needed and to evenly wear out flash memory. The policy uses a fine-grained method to effectively cluster hot data and cold data in order to reduce cleaning overhead. A wear-leveling algorithm is also proposed. Performance evaluations show that erase operations are significantly reduced and flash memory is evenly worn, Though the proposed fine-grained separation scheme is targeted at flash memory-based systems, it can be applied to other storage systems as well. (C) 1999 Elsevier Science Inc. All rights reserved.
EJVM: an economic Java run-time environment for embedded devices
(2001-02-01)
Chang, DW
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Chang, RC
;
資訊工程學系
;
Department of Computer Science
As network-enabled embedded devices and Java grow in their popularity, embedded system researchers start seeking ways to make these devices Java-enabled. However, it is a challenge to apply Java technology to these devices due to their shortage of resources. In this paper, we propose EJVM (Economic Java Virtual Machine), an economic way to run Java programs on network-enabled and resource-limited embedded devices. Espousing the architecture proposed by distributed JVM, we store all Java codes on the server to reduce the storage needs of the client devices. In addition, we use two novel techniques to reduce the client-side memory footprints: server-side class representation conversion and on-demand bytecode loading. Finally, we maintain client-side caches and provide performance evaluation on different caching policies. We implement EJVM by modifying a freely available JVM implementation, Kaffe. From the experiment results, we show that EJVM can reduce Java heap requirements by about 20-50 % and achieve 90 % of the original performance. Copyright (C) 2001 John Wiley & Sons, Ltd.
A Server-side Pre-linking Mechanism for Updating Embedded Operating System Dynamically
(2010-01-01)
Shen, Bor-Yeh
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Chiang, Mei-Ling
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資訊工程學系
;
Department of Computer Science
To allow embedded operating systems to update their components on-the-fly, dynamic update mechanism is required For operating systems to be patched or added extra functionalities in without the need of rebooting the machines However. embedded environments are usually resource-limited in terms of memory size, processing power, power consumption, and network bandwidth Thus. dynamic update for embedded operating systems should be designed to make the best use of limited resources In this paper, a server-side pre-linking mechanism is proposed to make dynamic updates of embedded operating system efficiently Applying this mechanism can reduce not only memory usage and CPU processing time for dynamic update, but also data transmission size for updated components Power consumption can be reduced as well We have implemented this mechanism in LyraOS which is a component-based embedded operating system Performance evaluation shows that the size of updated components applying the proposed dynamic update mechanism can be 65-86% smaller than applying the approach of Linux loadable kernel modules Especially, the overheads in embedded clients are minimal since the component linking time in embedded clients is eliminated
Performance Evaluation of Inter-Processor Communication for an Embedded Heterogeneous Multi-Core Processor
(2012-05-01)
Tsao, Shiao-Li
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Lee, Sung-Yuan
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資訊工程學系
;
Department of Computer Science
Embedded systems often use a heterogeneous multi-core processor to improve performance and energy efficiency. This multi-core processor is composed of a general purpose processor (GPP), which manages the program flow and I/O, and a digital. signal processor (DSP), which processes mass data. An inter-processor communication (IPC) mechanism is thus required to exchange data between a GPP and a DSP. This paper uses comprehensive experiments to evaluate the IPC performance of an embedded heterogeneous multi-core processor under different design strategies. We further develop the IPC performance model and suggest dynamic adjustment of IPC strategies under environmental parameters and system resource constraints. Based on the results and findings, we improve the IPC performance of a voice over IP (VoIP) phone. Experimental results demonstrate that the GPP workload decreases significantly by 35% without sacrificing the functionalities and voice quality of the VolP system. Moreover, we apply the concept of dynamic adjustment of IPC strategies to an embedded media gateway. The simulation results demonstrate that the dynamic IPC strategy can considerably improve the system performance of the media gateway compared with the static IPC design approach.
A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security
(2012-05-01)
Cheng, Chieh-Jen
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Wang, Chao-Ching
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Ku, Wei-Chun
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Chen, Tien-Fu
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Wang, Jinn-Shyan
Contemporary network security applications generally require the ability to perform powerful pattern matching to protect against attacks such as viruses and spam. Traditional hardware solutions are intended for firewall routers. However, the solutions in the literature for firewalls are not scalable, and they do not address the difficulty of an antivirus with an ever-larger pattern set. The goal of this work is to provide a systematic virus detection hardware solution for network security for embedded systems. Instead of placing entire matching patterns on a chip, our solution is a two-phase dictionary-based antivirus processor that works by condensing as much of the important filtering information as possible onto a chip and infrequently accessing off-chip data to make the matching mechanism scalable to large pattern sets. In the first stage, the filtering engine can filter out more than 93.1% of data as safe, using a merged shift table. Only 6.9% or less of potentially unsafe data must be precisely checked in the second stage by the exact-matching engine from off-chip memory. To reduce the impact of the memory gap, we also propose three enhancement algorithms to improve performance: 1) a skipping algorithm; 2) a cache method; and 3) a prefetching mechanism.
Modeling and analysis of core-centric network processors
(2008-07-01)
Lin, Yi-Neng
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Lin, Ying-Dar
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Lai, Yuan-Cheng
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Tseng, Kuo-Kun
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交大名義發表
Network processors can be categorized into two types, the coprocessors-centric model in which data-plane is handled by coprocessors, and the core-centric model in which the core processes most of the data-plane packets yet offloading some tasks to coprocessors. While the former has been properly explored over various applications, research regarding the latter remain limited. Based on the previous experience of prototyping the virtual private network (VPN) over the IXP425 network processor, this work aims to derive design implications for the core-centric model performing computational intensive applications. From system and IC vendors' perspectives, the continuous-time Markov chain and Petri net simulations are adopted to explore this architecture. Analytical results prove to be quite inline with those of the simulation and implementation. With subsequent investigation, we find that appropriate process run lengths can improve the effective core utilization by 2.26 times, and by offloading the throughput boosts 7.5 times. The results also suggest single-process programming, since context-switch overhead impacts considerably on the performance.
Modeling and Analysis of Core-Centric Network Processors
(2009-01-01)
Lin, Yi-Neng
;
Lin, Ying-Dar
;
Tseng, Kuo-Kun
;
Lai, Yuan-Cheng
;
交大名義發表
Network processors can be categorized into two types, the coprocessors-centric model in which the data-plane is handled by coprocessors, and the core-centric model in which the core processes most of the data-plane packets yet offloading some tasks to coprocessors. While the former has been properly explored over various applications, researches regarding the latter remain limited. Based on the previous experience of prototyping the virtual private network (VPN) over the IXP425 network processor, this work aims to derive design implications for the core-centric model performing computational intensive applications. From system and IC vendors' perspectives, the continuous-time Markov chain and Petri net simulations are adopted to explore this architecture. Analytical results prove to be quite inline with those of the simulation and implementation. With subsequent investigation we find that appropriate process run lengths can improve the effective core utilization by 2.26 times, and by offloading the throughput boosts 7.5 times. The results also suggest single process programming since context switch overhead impacts considerably on the performance.
An Embedded Mobile ECG Reasoning System for Elderly Patients
(2010-05-01)
Shih, Dong-Her
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Chiang, Hsiu-Sen
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Lin, Binshan
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Lin, Shih-Bin
;
資訊管理與財務金融系註：原資管所+財金所
With the increase in the number senior citizens and chronic diseases, the number of elderly patients who need constant assistance has increased. One key point of all critical care for elderly patient is the continuous monitoring of their vital signs. Among these, the ECG signal is used for noninvasive diagnosis of cardiovascular diseases. Also, there is a pressing need to have a proper system in place for patient identification. Errors in patient identification, and hence improper administration of medication can lead to disastrous results. This paper proposes a novel embedded mobile ECG reasoning system that integrates ECG signal reasoning and RF identification together to monitor an elderly patient. As a result, our proposed method has a good accuracy in heart beat recognition, and enables continuous monitoring and identification of the elderly patient when alone. Moreover, in order to examine and validate our proposed system, we propose a managerial research model to test whether it can be implemented in a medical organization. The results prove that the mobility, usability, and performance of our proposed system have impacts on the user's attitude, and there is a significant positive relation between the user's attitude and the intent to use our proposed system.

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