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Effects of methyl silsesquioxane electron-beam curing on device characteristics of logic and four-transistor static random-access memory
(1999-11-01)
Lin, CF
;
Tung, IC
;
Feng, MS
;
材料科學與工程學系
;
Department of Materials Science and Engineering
The as-spun methyl silsesquioxane (MSQ) film cured by an electron beam (e-beam) did not show water absorption after a five-day exposure to ambient ail: MSQ was applied to the triple-level metal (TLM) Logic and double-level metal (DLM) foul-transistor (4-T) static random-access memory (SRAM) as intermetal dielectric by means of the non-etchback process. When MSQ treatment conditions were properly controlled, the top layer of the as-spun films was cured by e-beam exposure while the bottom layer of the film was thermally cured for a short period of time. The as-cured MSQ offered good surface planarity. In addition, neither via poisoning, bowing nor cracking was observed. The results showed that, by the application of the e-beam cured MSQ in the fabrication of intel connect structures, the cache time of DLM 4-T SRAM could be improved to 10 ns compared with 11.5 ns for the SRAM fabricated using the conventional furnace cure spin-on-glass (SOG) process (400 degrees C annealing for one hour). E-beam exposure has little effect on n-channel metal-oxide-semiconductor (NMOS) device characteristics, such as saturation current threshold voltage and channel length. In contrast, e-beam exposure has a significant effect on p-channel MOS (PMOS) device characteristics, resulting in a shift of the threshold voltage as well as an increase in the channel length. It is notable that the e-beam exposure almost did not affect NMOS device characteristics in the 4-T SRAM, since the polysilicon load resistor could serve as a shield against electron bombardment. In such a case, the resistance of the polysilicon load resistor was significantly decreased.
Effectively blocking copper diffusion at low-k hydrogen silsesquioxane/copper interface
(1999-11-01)
Liu, PT
;
Chang, TC
;
Yang, YL
;
Cheng, YF
;
Shih, FY
The interaction between copper and low-k hydrogen silsesquioxane (HSQ) film was investigated using a Cu/HSQ/Si metal insulation semiconductor capacitor and hydrogen plasma posttreatment. Owing to serious diffusion of copper atoms in HSQ film, degradation of the dielectric properties are significant with the increase of thermal stress. By applying hydrogen plasma treatment to the HSQ film, however, the phenomena of serious Cu penetration were not observed by electrical characteristic measurements and secondary ion mass spectroscopy (SIMS) analysis even in the absence of diffusion barrier layers. Therefore, hydrogen plasma treatment can effectively block the diffusion of copper in low-k HSQ film.
ESD protection under grounded-up bond pads in 0.13 mu m eight-level copper metal, fluorinated silicate glass low-k intermetal dielectric CMOS process technology
(2001-07-01)
Chou, KY
;
Chen, MJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Electrostatic discharge (ESD) protection device under the grounded-up bond pad is investigated in 0.13 mum full eight-level copper metal CMOS process technology with fluorinated silicate glass (FSG) low-k intermetal dielectric (IMD). The bonding force and power produces no cracking and no noticeable change in the second breakdown trigger point (V-t2, I-t2). High current I-V measured from the different level metal layers stack structures shows that 1) I-t2 depends very weakly on metal layers used, as expected due to certain junction power dissipation criterion and 2) V-t2 increases with the number of metal layers. The origin of the latter is increased dynamic impedance for increased metal layer number, as clarified by a simple RC model. The model also yields the intrinsic second breakdown trigger current and voltage for the underlying ESD protection device. Successfully configuring ESD protection circuits under the bond pads, therefore, not only is wholly free from the traditional area consumption, but also can substantially relax design constraints, enabling much more flexible and robust ESD schemes for various applications.
Active circuit's under wire bonding I/O, pads in 0.13 mu m eight-level Cu metal, FSG low-K inter-metal dielectric CMOS technology(+)
(2001-10-01)
Chou, KY
;
Chen, MJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Active circuits in terms of ring oscillator are moved to the place under the wire bonding pads in 0.13 mum fall eight-level copper metal complementary metal-oxide-semiconductor process with fluorinated silicate glass low-k inter-metal dielectric. The bond pad with the 12 K Angstrom thick aluminum metal film. as a bonding mechanical stress buffer layer is deposited on the topmost copper metal layer. No noticeable degradations in gate delay or cycle time of ring oscillator are detected in a variety of test structures subjected to bonding mechanical stress and thermal cycling stress. This indicates that the underlying process technology may be reliable and manufacturable in placing active circuits under the bonding pads and thereby the die area utility is recovered fully. More evidence is created from transmission fine pulsing experiments as well as capacitive-coupling experiments.
Effectiveness of NH3 plasma treatment in preventing wet stripper damage to low-k hydrogen silsesquioxane (HSQ)
(2001-12-01)
Chang, TC
;
Mor, YS
;
Liu, PT
;
Tsai, TM
;
Chen, CW
Wet stripper is commonly used to remove photoresist in IC integration processing. However, the high alkalinity of the wet stripper solution often leads to the hydrolysis of hydrogen silsesquioxane (HSQ) film and induces water uptake. As a result, both the leakage current and dielectric constant of HSQ increase. In this study, NH3 plasma treatment was applied to the HSQ film to form a thin nitrogen-containing layer on the HSQ surface and prevents the hydrolysis of HSQ during photoresist stripping. Dielectric degradation can be prevented by NH3 plasma treatment.
Active devices under CMOS I/O pads
(2002-12-01)
Chou, KY
;
Chen, MJ
;
Liu, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Active devices, including electrostatic discharge protection devices and ring-oscillator circuits, under CMOS I/O pads are investigated in a 130 nm full eight-level copper metal complementary metal-oxide-semiconductoir process, using fluorinated silicate glass (FSG) low-k inter-metal dielectric. The high current I-V curve measured in the second breakdown trigger point (V-t2, I-t2) of ESD protection devices under various metal level stack structures, shows that i) I-t2 depends very weakly on the number of metal levels used, as expected given specific junction power dissipation criteria; and ii) V-t2 increases with the number of metal level stacks of I/O pads because of increased dynamic impedance due to the presence of more metal levels, as clarified by a simple RC model. Moreover, no noticeable degradation in the speed of the ring-oscillator circuit, as measured for a variety of test structures subjected to bonding mechanical stress, thermal stress by temperature cycling and dc electrical stress by transmission line pulse, as well as ac electrical stress by capacitive-coupling experiments. Accordingly, active devices under CMOS I/O pads is independent of bonding pad metal level structures.
The novel pattern method of low-k hybrid-organic-siloxane-polymer film using X-ray exposure
(2002-12-02)
Chang, TC
;
Tsai, TM
;
Liu, PT
;
Mor, YS
;
Chen, CW
An organic low dielectric constant (low-k) material, hybrid-organic-siloxane-polymer. (HOSP), is integrated into multilevel interconnection using X-ray exposure technology. In conventional IC integration processes, photoresist (PR) stripping with O-2 plasma and wet chemical stripper is an inevitable step. However, dielectric degradation often occurs when low-k dielectrics undergo the PR stripping process. This limits the application of incorporating low-k material into semiconductor fabrication. In order to overcome the integration issue, a novel pattern method, X-ray direct patterning is proposed. In this technology, the dielectric regions illuminated by X-ray will be cross-linked, forming the desired patterns. At the same time, the regions without X-ray illumination are dissolvable in a solvent of HOSP film. Direct-patterning processes have several advantages: (1) they do not need PR to define patterns; thereby the damage from PR stripping can be eliminated, (2) the complex etching on low-k dielectrics can be eliminated, (3) the process steps are simplified. In this work, we will investigate the dielectric properties of HOSP film with X-ray curing for the first time. Additionally, a scanning electron microscope image of circle pattern was made to verify the process practicability. (C) 2002 Elsevier Science B.V. All rights reserved.
Investigation of the electrical properties and reliability of amorphous SiCN
(2004-01-30)
Chen, CW
;
Chang, TC
;
Liu, PT
;
Tsai, TM
;
Huang, HC
Amorphous SiCN (a-SiCN) is a candidate for barrier dielectric and has lower dielectric constant (ksimilar to5) relative to the commonly used barrier SiN (ksimilar to7). In this study, we investigate the leaky behavior and barrier characteristics of a-SiCN (k: 4similar to5) doped with different nitrogen concentration. The leaky behavior of a-SiCN is Poole-Frenkel at high electric field. This is similar to SiN. Thermal stability of a-SiCN films is good enough to meet the prescription in back-end-of-line fabrication process. The bias-temperature stress (BTS) test has been conducted on a-SiCN to investigate the barrier ability against copper 15/16penetration. We find that a-SiCN could sustain the stress of electric field up to 4 mV/cm at 150 degreesC. In addition, a-SiCN films with higher nitrogen concentration exhibit better barrier property against copper penetration. The SIMS spectra also have been used to monitor the distributions of copper after different BTS conditions, confirming our inference on leakage mechanism. (C) 2003 Elsevier Science B.V. All rights reserved.
Extraction of electrical mechanisms of low-dielectric constant material MSZ for interconnect applications
(2004-01-30)
Chang, TC
;
Yan, ST
;
Liu, R
;
Lin, ZW
;
Aoki, H
In this paper, electrical characterization of low-k dielectric methyl-silsesquiazane (MSZ) is presented. Thermal stress and bias temperature stress (BTS) were utilized to evaluate the impact of Cu penetration on dielectric properties. In the investigation of thermal stress performed by furnace annealing, the leakage mechanism of Al- and Cu-gate MIS capacitors is competed by the decrease of the interfacial states between metal and dielectric and the increase of defects resulted from Cu penetration. Also, the leakage conduction mechanism at high electric field is deduced from Schottky emission in conjunction with space-charge-limited current conduction (SCLC) through BTS methods. (C) 2003 Elsevier B.V. All rights reserved.
Effect of carrier gas on the structure and electrical properties of low dielectric constant SiCOH film using trimethylsilane prepared by plasma enhanced chemical vapor deposition
(2004-12-22)
Cheng, YL
;
Wang, Y
;
Lan, JK
;
Chen, HC
;
Lin, JH
For a low dielectric constant inter-metal dielectric application, the low-k SiCOH film with a dielectric constant of 2.8-3.2 has been deposited by plasma-enhanced chemical vapor deposition (PE-CVD) with trimethylsilane (3MS), oxygen, and the carrier gas. In this work, we present the effects of the carrier gas on the characterizations of the low-k films, including reaction mechanism, the deposition rate, and the mechanical and electrical properties. According to the experimental results, the low-k film in Ar carrier gas exhibits the improvement in deposition rate, nonuniformity, leakage current, and hardness. In addition, the dielectric constant of the deposited low-k film is slightly sacrificed due to the decrease of micropores in the deposited films. (C) 2004 Elsevier B.V. All rights reserved.

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