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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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    Novel program versus disturb window characterization for split-gate flash cell
    (2005-03-01)
    Sung, HC
    ;
    Lei, TF
    ;
    Hsu, TH
    ;
    Kao, YC
    ;
    Lin, YT
    In this letter, a new methodology for program versus disturb window characterization on split gate Flash cell is presented for the first time. The window can be graphically illustrated in V-wI (word-line)-V-ss (source) domain under a given program current. This method can help us understand quantitatively how the window shifts versus bias conditions and find the optimal program condition. The condition obtained by this method can have the largest tolerance for program, bias variations. This methodology was successfully implemented in 0.18-mum triple self-aligned (SA3) split-gate cell characterization to provide program condition for 32 M products.
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    A novel program-erasable high-(K) A1N-Si MIS capacitor
    (2005-03-01)
    Lai, CH
    ;
    Chin, A
    ;
    Hung, BF
    ;
    Cheng, CF
    ;
    Yoo, WJ
    We demonstrate a programmable-erasable MIS capacitor with a single layer high-kappa AIN dielectric on Si having a high capacitance density of 5 fF/mum(2). It has low program and erase voltages of +4 and -4 V, respectively. Such an erase function is not available in other single layer Al2O3, AION, or other known high-kappa dielectric capacitors, where the threshold voltage (T h) shifts continuously with voltage. This device exhibits good data retention with a V-th change of only 0.06 V after 10 000 s.
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    A program-erasable high-k Hf0.3N0.2O0.5 MIS capacitor with good retention
    (2007-10-01)
    Yang, H. J.
    ;
    Chin, Albert
    ;
    Chen, W. J.
    ;
    Cheng, C. F.
    ;
    Huang, W. L.
    We describe a programmable-erasable MIS capacitor with a single high-kappa Hf0.3N0.2O0.5 dielectric layer. This device showed a capacitance density of similar to 6.6 fF/mu m(2), low program and erase voltages of +5 and -5 V, respectively, and a large Delta V-fb memory window of 1.5 V. In addition, the 25 degrees C data retention was good, as indicated by program and erase decay rates of only 2 and 6.2 mV/dec, respectively. Such device retention is attributed to the deep trapping level of 1.05 eV in the Hf0.3N0.2O0.5.
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    Comparison of MONOS memory device integrity when using Hf(1-x-y)N(x)O(y) trapping layers with different N compositions
    (2008-06-01)
    Yang, H. J.
    ;
    Cheng, C. F.
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    Chen, W. B.
    ;
    Lin, S. H.
    ;
    Yeh, F. S.
    We have studied the nitrogen composition dependence of the characteristics of TaN/HfLaON/Hf(1-x-y)N(x)O(y)/ SiO(2)/Si MONOS memory devices. By increasing the N composition in the Hf(1-x-y)N(x)O(y) trapping layer, both the memory window And high-temperature retention improved. The Hf(0.3)N(0.2)O(0.5) MONOS device displayed good characteristics in terms of its +/-9-V program/erase (P/E) voltage, 100-mu s P/E speed, large initial 2.8-V memory window, and a ten-year extrapolated retention of 1.8 V at 85 degrees C or 1.5 V at 125 degrees C.
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    Improving the retention and endurance characteristics of charge-trapping memory by using double quantum barriers
    (2008-07-01)
    Lin, S. H.
    ;
    Yang, H. J.
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    Chen, W. B.
    ;
    Yeh, F. S.
    ;
    McAlister, Sean P.
    We have studied the performance of double-quantum-barrier [TaN - Ir(3)Si] - [HfAlO - LaAlO(3)] - Hf(0.3)N(0.2)O(0.5) - [HfAlO - SiO(2)]-Si charge-trapping memory devices. These devices display good characteristics in terms of their +/- 9-V program/erase (P/E) voltage, 100-mu s P/E speed, initial 3.2-V memory window, and ten-year extrapolated data retention window of 2.4 V at 150 degrees C. The retention decay rate is significantly better than single-barrier MONOS devices, as is the cycled retention data, due to the reduced-interface trap generation.