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Design of ESD Protection Diodes With Embedded SCR for Differential LNA in a 65-nm CMOS Process
(2014-11-01)
Lin, Chun-Yu
;
Fan, Mei-Lian
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The pin-to-pin electrostatic discharge (ESD) issue for a differential low-noise amplifier (LNA) was studied in this work. A new design of ESD protection diodes with an embedded silicon-controlled rectifier (SCR) was proposed to protect the gigahertz differential LNA. The proposed ESD protection design was modified from the conventional ESD protection design without adding any extra device. The SCR path was established directly from one differential input pad to the other differential input pad so the pin-to-pin ESD robustness can be improved. This design had been verified in a 65-nm CMOS process. Besides, this design had been further applied to a 24-GHz LNA in the same 65-nm CMOS process. Experimental results had shown that the proposed ESD protection design for the differential LNA can achieve excellent ESD robustness and good RF performances.
Low-capacitance SCR with waffle layout structure for on-chip ESD protection in RF ICs
(2008-05-01)
Ker, Ming-Dou
;
Lin, Chun-Yu
;
電機學院
;
College of Electrical and Computer Engineering
The silicon-controlled rectifier (SCR) has been used as an effective on-chip electrostatic discharge (ESD) protection device in CMOS technology due to the highest ESD robustness in nanoscale integrated circuits (10). In this study, the SCR realized in a waffle layout structure is proposed to improve ESD current distribution efficiency for ESD protection and to reduce the parasitic capacitance. The waffle layout structure of the SCR can achieve smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to ESD protection devices can be reduced. The proposed waffle SCR with low parasitic capacitance is suitable for on-chip ESD protection in RF ICs. Besides, the desired current to trigger on the SCR device with a waffle layout structure and its turn-on time has also been investigated in a silicon chip.
Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface
(2002-06-01)
Ker, MD
;
Chuang, CH
;
電機學院
;
College of Electrical and Computer Engineering
A stacked-NMOS triggered silicon-controlled rectifier (SNTSCR) is proposed as the electrostatic discharge (ESD) clamp device to protect the mixed-voltage I/O buffers of CMOS ICs. This SNTSCR device is fully compatible to general CMOS processes without using the thick gate oxide to overcome the gate-oxide reliability issue. ESD robustness of the proposed SNTSCR device with different layout parameters has been investigated in a 0.35-mum CMOS process. The HBM ESD level of the mixed-voltage I/O buffer with the stacked-NMOS channel width of 120 mum can be obviously improved from the original similar to2 kV to be greater than 8 kV by this SNTSCR device with a device dimension of only 60 mum/0.35 mum.
Latchup-free ESD protection design with complementary substrate-triggered SCR devices
(2003-08-01)
Ker, MD
;
Hsu, KC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V-SS and pad-to-V-DD ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-mum salicided CMOS process with the human body model (machine model) ESD level of similar to7.25 kV (500 V) in a small layout area.
SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes
(2003-09-01)
Ker, MD
;
Hsu, KC
;
電機學院
;
College of Electrical and Computer Engineering
Turn-on efficiency is the main concern for silicon-controlled rectifier (SCR) devices used as on-chip electrostatic discharge (ESD) protection circuit, especially in deep sub-quarter-micron CMOS processes with much thinner gate oxide. A novel double-triggered technique is proposed to speed up the turn-on speed of SCR devices for using in on-chip ESD protection circuit to effectively protect the much thinner gate oxide in sub-quarter-micron CMOS processes. From the experimental results, the switching voltage and turn-on time of such double-triggered SCR (DT_SCR) device has been confirmed to be significantly reduced by this double-triggered technique.
SCR device with dynamic holding voltage for on-chip ESD protection in a 0.25-mu m fully salicided CMOS process
(2004-10-01)
Ker, MD
;
Chen, ZP
;
電機學院
;
College of Electrical and Computer Engineering
A dynamic-holding-voltage silicon-controlled rectifier (DHVSCR) device is proposed and verified in a 0.25-mum/2.5-V salicided CMOS process. In the DHVSCR device structure, the control nMOS and pMOS transistors are directly embedded in SCR device structure. The proposed DHVSCR device has the characteristics of tunable holding voltage and holding current by changing the gate voltage of embedded nMOS and pMOS. Under normal circuit operating condition, the DHVSCR has a holding voltage higher than the supply voltage without causing a latch-up issue. Under an electrostatic discharge (ESD) stress condition, the DHVSCR has a lower holding voltage to effectively clamp the overshooting ESD voltage. From the experimental results, the DHVSCR with a device width of 50 mum can sustain a human-body-model ESD level of 5.6 kV.
On-Chip Transient Voltage Suppressor Integrated With Silicon-Based Transceiver IC for System-Level ESD Protection
(2014-10-01)
Chuang, Che-Hao
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel on-chip transient voltage suppressor (TVS) integrated with the silicon-based transceiver IC has been proposed and verified in a 0.8 mu m bipolar CMOS DMOS (BCD) process for IEC 61000-4-2 system-level electrostatic discharge (ESD) protection. The structure of on-chip TVS is a high-voltage dual silicon-controlled rectifier (DSCR) with +/- 16 V of high holding voltage (Vh) under the evaluation of the transmission line pulsing (TLP) system with the pulse width of 100 ns. With the high holding current (Ih) of on-chip TVS, this design can pass +/- 200 mA latch-up testing. Therefore, the on-chip TVS can be safely applied to protect the RS232 transceiver with the signal level of +/- 15 V. The RS232 transceiver IC with on-chip TVS has been evaluated to pass the IEC61000-4-2 contact +/- 12 kV stress without any hardware damages and latch-up issue. Moreover, the proposed RS232 transceiver IC has been verified to well protect the system over the IEC 61000-4-2 contact +/- 20 kV stress (class B) in the notebook applications.
Semiself-Protection Scheme for Gigahertz High-Frequency Output ESD Protection
(2011-07-01)
Lee, Jian-Hsing
;
Huang, Shao-Chang
;
Su, Hung-Der
;
Chen, Ke-Horng
;
電控工程研究所
In this paper, a semiself-protection scheme is proposed and developed for gigahertz output electrostatic-discharge (ESD) protection. The output transistor acts as a trigger device to trigger the ESD protection device, and then, it is turned off when the ESD protection device turns on. Thus, the capacitance of a gigahertz high-frequency output pad can be minimized because this scheme is without any additional trigger device or any passive component.
A Latchup-Immune and Robust SCR Device for ESD Protection in 0.25-mu m 5-V CMOS Process
(2013-05-01)
Huang, Yu-Ching
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Based on good electrostatic discharge (ESD) robustness, silicon-controlled rectifier (SCR) device is used for on-chip ESD protection. The major concern of SCR is the latch-up issue, because of its low holding voltage. Previous papers tried to design latchup-immune SCR devices; however, those devices would cause lower ESD robustness. In this letter, a new latchup-immune and robust SCR device for ESD protection is proposed and verified in a 0.25-mu m 5-V CMOS process. Through inserting one additional parasitic bipolar junction transistor into SCR device structure, this new proposed SCR can increase the holding voltage without causing degradation on its ESD robustness.
Large-Swing-Tolerant ESD Protection Circuit for Gigahertz Power Amplifier in a 65-nm CMOS Process
(2013-02-01)
Lin, Chun-Yu
;
Tsai, Shiang-Yu
;
Chu, Li-Wei
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
The signal swing at output pad of some radio-frequency (RF) power amplifiers (PAs) may be higher than the supply voltage. To protect the gigahertz large-swing power amplifier from electrostatic discharge (ESD) damage in nanoscale CMOS process, a large-swing-tolerant ESD protection circuit is presented in this paper. The proposed ESD protection circuit had been designed, fabricated, and characterized in a 65-nm CMOS process, where it can achieve low parasitic capacitance, large swing tolerance, high ESD robustness, and good latchup immunity. The proposed ESD protection circuit had been further applied to a 2.4-GHz PA to provide 3-kV human-body-model (HBM) ESD robustness without degrading the RF performances.

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