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Access type: Open accessSubject: search.filters.subject.thin-film transistor

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Now showing 1 - 10 of 17
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    Fabrication and Characterization of Film Profile Engineered ZnO TFTs With Discrete Gates
    (2015-05-01)
    Lyu, Rong-Jhe
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    Lin, Horng-Chih
    ;
    Huang, Tiao-Yuan
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    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    By virtue of the film-profile engineering scheme and properly designed device structure, ZnO TFTs with discrete bottom gates and sub-micron channels were fabricated and characterized. In the fabrication, a suspended bridge constructed over the bottom gate is used to tailor the profile of subsequently deposited films. Superior electrical characteristics in terms of ultrahigh ON/OFF current ratio (similar to 10(10)), steep sub-threshold swing (66 similar to 108 mV/dec), and very low off-state leakage current are demonstrated with the fabricated devices. Effects of channel lengths on the device characteristics are also explored. Because of more effective shadowing of the depositing species with a longer suspended bridge, the deposited films become thinner at the central channel. As a result, the device shows more positive turn-on voltage and better subthreshold swing with increasing channel length.
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    Comparison of N-2 and NH3 plasma passivation effects on polycrystalline silicon thin-film transistors
    (1998-07-01)
    Lee, YS
    ;
    Lin, HY
    ;
    Lei, TF
    ;
    Huang, TY
    ;
    Chang, TC
    The passivation effects of pure N-2 plasma on polycrystalline silicon (poly-Si) thin-film transistors (TFTs) have been studied and compared with those of NH3 plasma. We found that, similar to the recently-proposed NH3 plasma passivation, N-2 plasma passivation can also effectively improve device parameters such as field effect mobility, threshold voltage subthreshold swing, off current, and on/off current ratio. While the improvement of NH3-passivated devices can be attributed to both hydrogen and nitrogen passivation effects, nitrogen passivation alone is mainly responsible for the improvement of N-2-passivated devices. Zn addition, we round that N-2-passivated devices exhibit much better hot-carrier reliability than NH3-passivated devices. The better hot-carrier reliability of N-2-passivated devices can be explained by the formation of strong Si-N bonds which are difficult to break, while effectively eliminating the weaker N-H bonds, which are inevitable in NH3-passivated devices. The results of a Fourier. transform infrared (FTIR) spectrum analysis performed in this study are consistent with this proposition.
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    Hydrogenation of polysilicon thin-film transistor in a planar inductive H-2/Ar discharge
    (1999-05-01)
    Yeh, CF
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    Chen, TJ
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    Liu, C
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    Gudmundsson, JT
    ;
    Lieberman, MA
    A planar inductive discharge is used to hydrogenate polysilicon thin-film transistors (poly-Si TFT's). Experimental results indicate that inductive discharges operate at higher plasma densities, thereby capable of shortening the hydrogenation time. In addition, to promote the ionization of hydrogen, Ar gas is also introduced to H-2 plasma during hydrogenation. Furthermore, me discuss the mechanism of Ar enhanced hydrogenation and the characteristics of H-2/Ar mixed plasma. Moreover, the posthydrogenation anneal is utilized to further enhance passivation efficiency and improve the reliability of poly-Si TFT's.
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    A novel thin-film transistor with self-aligned field induced drain
    (2001-01-01)
    Lin, HC
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    Yu, CM
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    Lin, CY
    ;
    Yeh, KL
    ;
    Huang, TY
    In this letter, a novel thin-film transistor with a self-aligned field-induced-drain (SAFID) structure is reported for the first time. The new SAFID TFT features a self-aligned sidewall spacer located on top of the drain offset region to set its effective length, and a bottom gate (or field plate) situated under the drain offset region to electrically induce the field-induced-drain (FID). So, unlike the conventional off-set-gated TFTs with their effective FID length set by two separate photolithographic masking layers, the new SAFID is totally immune to photomasking misalignment errors, while enjoying the low off-state leakage as well as high turn-on characteristics inherent in the FID structure. Polycrystalline silicon TFTs with the new SAFID structure have been successfully fabricated with significant improvement in the on/off current ratio.
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    Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain extension
    (2001-04-01)
    Lin, HC
    ;
    Yeh, KL
    ;
    Huang, RG
    ;
    Lin, CY
    ;
    Huang, TY
    A novel Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain (FID) extension is proposed and demonstrated. In the new device configuration, a metal field-plate (or sub-gate) lying on the passivation oxide is employed to induce a sheet of carriers in a channel offset region located between the silicided drain and the active channel region underneath the main-gate. The new device thus allows ambipolar device operation by simply switching the polarity of the bias applied to the field plate. In contrast to the conventional SBTFT that suffers from high GIDL (gate-induced drain leakage)-like off-state leakage current, the new SBTFT with FID is essentially free from the GIDL-like leakage current. In addition, unlike the conventional SBTFT that suffers from the low on-off current ratio, the new device exhibits high on/off current ratio up to 10(6) for both n- and p-channel modes of operation. Moreover, the implantless feature and the ambipolar capability of the new device also result in extra low mask count for CMOS processes integration. These excellent device characteristics, coupled with its simple processing, make the new device very promising for future large-area electronic applications.
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    Self-aligned fabrication of thin-film transistors with field-induced drain
    (2002-08-01)
    Yu, CM
    ;
    Lin, HC
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    Lin, CY
    ;
    Yeh, KL
    ;
    Huang, TY
    Thin-film transistor (TFT) devices with either a top or a bottom sub-gate were fabricated and characterized. The top sub-gate scheme allows the self-aligned formation of main-gate with respect to the sub-gate. On the other hand, the bottom sub-gate scheme features a self-aligned field-induced drain with a sidewall spacer located on its top to set the effective field-induction-drain (FID) length. Unlike the conventional TFTs, the FID serves to distribute the high drain electric field and thereby eliminates gate-induced drain leakage-like off-state leakage current. Superior device performance is realized with the bottom sub-gate structure. (C) 2002 Elsevier Science Ltd. All rights reserved.
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    A novel SiGe raised source/drain polycrystalline silicon thin-film transistor with improved on-current and larger breakdown voltage
    (2003-03-01)
    Peng, DZ
    ;
    Chang, TC
    ;
    Liu, CF
    ;
    Yeh, PH
    ;
    Liu, PT
    A novel poly-Si thin-film transistor with a self-aligned SiGe raised source/drain (SiGe-RSD TFT) has been proposed and fabricated. The SiGe-RSD regions were grown selectively by the ultra-high vacuum chemical vapor deposition (UHVCVD) process designed by us at 550degreesC. The resultant transistor structure features an ultra-thin active channel region (20 nm) and a self-aligned thick source/drain region (120 nm), and is ideally suited for optimum performance. Significant improvements in electrical characteristics, such as higher turn-on current, lower leakage current and higher drain breakdown voltage have been observed in the SiGe RSD TFT, compared to its conventional TFT counterpart. Moreover, the process is simple and no additional masks are necessary, which is consistent with conventional fabrication processes.
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    Fabrication and characterization of Schottky barrier polysilicon thin-film transistors with excimer-laser crystallized channel
    (2003-04-01)
    Yeh, KL
    ;
    Lin, HC
    ;
    Tsai, RW
    ;
    Lee, MH
    ;
    Huang, TY
    Schottky barrier thin-film transistors (SB TFT) with field-induced drain (FID) have recently been demonstrated to exhibit ambipolar capability with low off-state leakage current. In this study, we investigate and compare the characteristics of poly-Si SB TFTs with channel layer prepared by excimer laser crystallization (ELC) and solid-phase crystallization (SPC). It is shown that the use of ELC could greatly improve the device characteristics, comparing to the SPC counterparts. Excellent device performance with steep subthreshold slope and on/off current ratio higher than 10(8) for both p- and n-channel operations are demonstrated on a single device with ELC channel. The effects of sub-gate bias, channel length, and channel offset length, on device characteristics are also explored.
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    Device characteristics of polysilicon thin-film transistors fabricated by electroless plating Ni-induced crystallization of amorphous Si
    (2003-04-01)
    Chao, CW
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    Wu, YCS
    ;
    Hu, GR
    ;
    Feng, MS
    ;
    材料科學與工程學系
    Compared with conventional solid phase crystallized (SPC) thin-film transistors (TFTs), metal-induced laterally crystallized (MILL) TFTs exhibit significantly enhanced performance. Metal films are usually deposited by the physical vapor deposition (PVD) method, which is time-consuming and expensive in terms of equipment cost. In this work, a simpler electroless plating Ni was introduced to replace PVD Ni. It was found that the morphologies and the device characteristics of Ni-induced lateral crystallization TFT were as good as those of PVD Ni-induced lateral crystallization TFT.
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    Improved annealing process for electroless Pd plating induced crystallization of amorphous silicon
    (2003-08-01)
    Hu, GR
    ;
    Huang, TJ
    ;
    Wu, YS
    ;
    材料科學與工程學系
    ;
    Department of Materials Science and Engineering
    Electroless Pd plating induced crystallization of amorphous silicon (a-Si) thin films has been proposed for fabricating low-temperature polycrystalline silicon thin film transistors (LTPS TFTs). However, the current crystallization process often leads to poor device performance due to the large amount of I'd-silicide residues in the poly-Si thin films. It was found that the amount of I'd silicide increased with annealing time and temperature. In this study, a two-step annealing process was developed to obtain the appropriate amount of Pd silicide for inducing the crystallization of a-Si. The device characteristics were significantly improved by this two-step process.