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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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1993 - 19943

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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.CHANG, CYSubject: search.filters.subject.VLSI

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Now showing 1 - 3 of 3
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    THE BEHAVIOR OF BILATERAL LATCH-UP TRIGGERING IN VLSI ELECTROSTATIC DISCHARGE DAMAGE PROTECTION CIRCUITS
    (1993-11-01)
    HUANG, HS
    ;
    CHANG, CY
    ;
    HSU, CC
    ;
    CHEN, KL
    ;
    LIN, JK
    A new latch-up phenomenon that shows symmetrical diac I-V characteristics has been discovered recently. Electrical measurements show that a diac parasitic semiconductor-controlled-rectifier (SCR) device can exist between two adjacent electro static discharge damage (ESD) protection circuits or output buffers. The SCR consists of two parasitic P-N-P-N paths and can easily induce a localized SCR latch-up between two adjacent input or output terminals. This is not similar to traditional latch-up that creates a parasitic P-N-P-N path between power supply and ground pins, but is a new bilateral latch-up path between two adjacent input and output pins. A new latch-up failure mode due to this diac structure, which creates a bilateral path during temperature humidity bias (THB) testing, is discussed. Some suggestions regarding the improvement of this diac latch-up degradation are proposed. Advanced analyses and modeling are also presented in this paper. The modified diac latch-up lumped element model successfull explains this phenomenon.
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    A STUDY ON BILATERAL LATCH-UP SELF-TRIGGERING IN COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR PROTECTION CIRCUITS
    (1994-01-01)
    HUANG, HS
    ;
    CHANG, CY
    ;
    CHEN, KL
    ;
    LIU, IO
    ;
    HSU, CC
    The results of serial studies on the behavior of bilateral latch-up in complementary metal-oxide-semiconductor field effect transistor (CMOS) protection circuits are presented. Bilateral latch-up self-triggering resulting from serial resistance or serial inductance on V-dd or V-ss is discussed. Optimizing the layout and design of output buffers to improve product performance and reliability is also recommended. The studies on the behavior of bilateral latch-up in CMOS protection circuits are increasingly important since low-power applications are the future trend.
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    NEW LARGE-ANGLE TILT IMPLANTED DRAIN STRUCTURE - SURFACE COUNTER-DOPED-LIGHTLY DOPED DRAIN FOR HIGH HOT-CARRIER RELIABILITY
    (1994-07-01)
    CHOU, JW
    ;
    CHANG, CY
    ;
    HUANG, C
    ;
    HO, LT
    ;
    KO, J
    A new surface counterdoped-lightly doped drain (SCD-LDD) structure with large angle tilt (LAT) implantation is proposed in this study. This structure introduces an additional larger tilt angle and lower-energy BF2 implant after the n- implant, which counterdopes the n- surface concentration to achieve a gate/n- fully overlapped, buried and sloped n- region inside the gate edge. As a result, the lateral electric fields inside the gate edge are reduced and pushed deeper into the substrate. In addition to a reduction in substrate current, this profile also suppresses hot carrier injection by driving the current away from the surface and the maximum electric field; then it shifts the avalanche region further into the bulk Si. This consequently produces a more effective enhancement of hot carrier reliability than that of conventional LDD's and controlled large-angle-tilt implanted drains (LATID's) for submicron VLSI circuits under 5 V operation. In conclusion, this SCD-LDD provides one more degree of freedom in optimizing the n- region doping profiles as a new LATID structure.