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Finger-gate array quantum pumps: Pumping characteristics and mechanisms
(2004-08-01)
Chung, SW
;
Tang, CS
;
Chu, CS
;
Chang, CY
;
電子物理學系
We study the pumping effects, in both the adiabatic and nonadiabatic regimes, of a pair of finite finger-gate array (FGA) on a narrow channel. Connection between the pumping characteristics and associated mechanisms is established. The pumping potential is generated by ac biasing the FGA pair. For a single pair (N=1) of finger gates (FG's), the pumping mechanism is due to the coherent inelastic scattering of the traversing electron to its subband threshold. For a pair of FGA with pair number N>2, the dominant pumping mechanism becomes that of the time-dependent Bragg reflection. The contribution of the time-dependent Bragg reflection to the pumping is enabled by breaking the symmetry in the electron transmission when the pumping potential is of a predominant propagating type. This propagating wave condition can be achieved both by an appropriate choice of the FGA pair configuration and by the monitoring of a phase difference phi between the ac biases in the FGA pair. The robustness of such a pumping mechanism is demonstrated by considering a FGA pair with only pair number N=4.
A novel structure for three-dimensional silicon magnetic transducers to improve the sensitivity symmetry
(1996-09-01)
Lin, HY
;
Lei, TF
;
Jeng, JJ
;
Pan, CL
;
Chang, CY
A three-dimensional silicon magnetic transducer with symmetric sensitivities in the x-, y- and z-directions and small cross sensitivity has been demonstrated. Devices are based on a design of a vertical Hall structure using the surrounding trench and symmetric design to suppress the cross sensitivity. The fabrication process is simple and can be used as a part of a standard integrated circuit process. The results show that almost equal sensitivities in all three components of magnetic field can be obtained by coating Ni/Co thin films on the backside of the substrates. The cross sensitivity is only 1.3% of the sensitivity.
A high-performance thin-film transistor with a vertical offset structure
(1996-12-01)
Chang, CY
;
Lin, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this study, we propose a novel device structure combined with conventional hydrogenated amorphous silicon (a-Si:H) for the source and drain regions and microcrystalline silicon (mu c-Si:H) for the channel region to obtain a high-performance thin-film transistor (TFT), This is a vertical a-Si:H offset structure used to suppress OFF-state current to a small value which is comparable to the conventional a-Si:H TFT's with a much higher drivability. The fabrication process is simple, low temperature (less than or equal to 300 degrees C), and low cost, with a potential for high reliability.
Resist-related damage on ultrathin gate oxide during plasma ashing
(1997-02-01)
Chien, CH
;
Chang, CY
;
Lin, HC
;
Chang, TF
;
Chiou, SG
This paper presents an important observation of plasma-induced damage on ultrathin oxides during O-2 plasma ashing by metal ''antenna'' structures with photoresist on top of the electrodes, It is found that for MOS capacitors without overlying photoresist during plasma ashing, only minor damage occurs on thin oxides, even for oxide thickness down to 4.2 nm and an area ratio as large as 10(4), In contrast, oxides thinner than 6 nm with resist overlayer suffer significant degradation from plasma charging, This phenomenon is contrary to most previous reports, It suggests that the presence of photoresist will substantially affect the plasma charging during ashing process, especially for devices with ultrathin gate oxides.
Reliability of strained SiGe channel p-channel metal-oxide-semiconductor field-effect transistors with ultra-thin (EOT=3.1nm) N2O-annealed SiN gate dielectric
(2005-06-01)
Chen, CW
;
Chien, CH
;
Chen, YC
;
Hsu, SL
;
Chang, CY
The p-channel metal-oxide-semi conductor field-effect transistor (pMOSFET) with 50-nm-thick Si0.85Ge0.15 channel and in ultra-thin (EOT = 3.1 nm) N2O-annealed SiN gate dielectric has been shown to have well-performing on/off and output characteristics. Several methodologies for the device reliability characterization, such as stress-induced-leakage-current (SILC), drain-avalanche-hot-carrier (DAHC) injection, channel hot-carrier (CHC) injection and negative-bias-temperature-instability (NBTI), have been used and the results were compared. In terms of the long-term degradation, the excellent quality of the N2O-annealed SiN gate dielectric can be firmly obtained because only negligible degradations have been found after stressing no matter which technique was employed. Even so, the experimental results have been compared and we found that the HC degradation is worse than the NBTI degradation and the channel-hot-carrier (CHC) stressing is the worst case for all kinds of reliability testing. Meanwhile, we have also verified that the interface state generation is the dominant mechanism responsible for the HC-induced degradation while the electron trapping dominates the device degradation for the NBTI stressing.
Electrical characteristics of thin HfO2 gate dielectrics prepared using different pre-deposition surface treatments
(2005-01-01)
Chen, CW
;
Chien, CH
;
Perng, TH
;
Yang, MJ
;
Liang, JS
We have investigated the effects that various pre-deposition surface treatments, such as HF dipping (HF-dipped), NH3 surface nitridation (NH3-annealed), and rapid thermal oxidation (RTO-treated), have on the electrical properties of HfO2 gate dielectrics. The NH3-annealed technique is superior to the others because the dielectric subject to NH3 surface nitridation possesses a tremendously reduced leakage current, the lowest equivalent oxide thickness (EOT),and a moderate, hysteresis width. In contrast, the RTO-treated preparation can only effectively reduce the leakage current by its resultant increased physical thickness and displays considerably severe hysteresis. We have also studied the dependence of hysteresis on the initial inversion bias (V-inv), temperature, and frequency for-all splits. The hysteresis width increases upon increasing the initial inversion bias and decreasing the temperature, but it is rather insensitive to the measuring frequency. In addition, our experimental results indicate that the hysteresis width depends exponentially on both the initial inversion bias and the temperature, and it can be described well by a general empirical relationship that has the form C(T) (.) exp(RvVinv,). Finally, the conduction currents through the dielectrics are probably dominated by trap-assisted tunneling (TAT) because the current densities display stronger temperature dependence at low voltage than they do at higher voltages. Based on the trap-assisted tunneling model, the corresponding parameters have been extracted and are presented.
The role of resist for ultrathin gate oxide degradation during O-2 plasma ashing
(1997-05-01)
Chien, CH
;
Chang, CY
;
Lin, HC
;
Chiou, SG
;
Huang, TY
During ashing process, resist has been intuitively regarded as a protection layer and deliberately removed in previous studies by wet process prior to plasma exposure in an effort to amplify the damage effect, Recently, we found instead that resist does not simply act as a protection layer, This newly observed phenomenon cannot be explained by the well-known electron shading effect which should not affect the area-intensive antenna structure used in our study, In this letter, we hypothesize that this resist-related charging damage is determined by the plasma potential adjustment difference between those devices with and without resist overlayer, The experimental results show a good correlation with our explanation, To be specific, severe antenna area ratio (ARR) dependent degradation of thin gate oxide is induced during the initial ashing stage while the resist is still on the electrodes, not during the overashing period.
A novel thin-film transistor with vertical offset structure
(1997-04-01)
Lin, CW
;
Chang, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel device structure consisting of conventional hydrogenated amorphous silicon (a-Si:H) for the source and drain and of hydrogenated microcrystalline soilicon (mu c-Si:H) for the channel region which can improve the performance of thin-film transistors (TFTs) has been proposed and fabricated. Undoped a-Si:H serves as a blocking layer to suppress the OFF-state current in the drain region which is comparable to that of conventional a-Si:H TFT with a much higher drivability. The fabrication process is simple and inexpensive e with the possibility of high reliability.
Effects of isolation oxides on undercut formation and electrical characteristics for silicon selective epitaxial growth
(1997-06-01)
Tseng, HC
;
Chang, CY
;
Pan, FM
;
Chen, LP
;
電子工程學系及電子研究所
Three isolation oxide structures have been prepared to study their resistance to the undercut formation during selective epitaxial growth (SEG) processes. The N2O annealed oxide tetraethyoxysilane (TEOS) oxide stacked structure has the best resistance to the undercut formation and exhibits the best electrical characteristics compared to the other two isolation oxide structures prepared in the study, which are a wet oxide and a TEOS oxide. This is ascribed to a smaller interfacial stress between the isolation oxide and the silicon substrate for the stacked structure. The sidewall damage is the predominant factor deteriorating the current-voltage (I-V) characteristics of the N+-P SEG diodes. When treated with a quick HF dip and followed by a low temperature desorption cleaning before the SEG process, the N+-P SEG diode, which has no perceivable undercut, shows satisfactory I-V characteristics.
Optoelectronic characteristics of alpha-SiC:H-based P-I-N thin-film light-emitting diodes with low-resistance and high-reflectance N+-alpha-SiCGe:H layer
(1997-09-01)
Chen, YA
;
Chiou, CF
;
Tsay, WC
;
Laih, LH
;
Hong, JW
The graded-gap a-SiC:II-based p-i-n thin-film light-emitting diodes (TFLED's) with an additional low-resistance and high-reflectance n(+)-a-SiCGe:H layer mere proposed and fabricated on indium-tin-oxide (ITO)-coated glass substrate in this paper. For a finished TFLED, a brightness of 720 cd/m(2) could be obtained at an injection current density of 600 mA/cm(2), and its EL (electroluminescence) threshold voltage was lowered to 8.6 V. in addition, the effects of reflectance and resistance of a-SiCGe:H film an the performance of TFLED were discussed, The optimum rapid thermal annealing (RTA) conditions for fabrication of TFLED after metallization were also studied and employed to improve the optoelectronic characteristics of TFLED.

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