<link rel="stylesheet" href="styles.cf390c6bfbe7555f.css"> Skip to main content

學術出版;;Publications

Permanent URI for this communityhdl:11536/1

收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作,涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

Browse

Search Results

Now showing 1 - 5 of 5
  • Item type:Item,
    Comparison of N-2 and NH3 plasma passivation effects on polycrystalline silicon thin-film transistors
    (1998-07-01)
    Lee, YS
    ;
    Lin, HY
    ;
    Lei, TF
    ;
    Huang, TY
    ;
    Chang, TC
    The passivation effects of pure N-2 plasma on polycrystalline silicon (poly-Si) thin-film transistors (TFTs) have been studied and compared with those of NH3 plasma. We found that, similar to the recently-proposed NH3 plasma passivation, N-2 plasma passivation can also effectively improve device parameters such as field effect mobility, threshold voltage subthreshold swing, off current, and on/off current ratio. While the improvement of NH3-passivated devices can be attributed to both hydrogen and nitrogen passivation effects, nitrogen passivation alone is mainly responsible for the improvement of N-2-passivated devices. Zn addition, we round that N-2-passivated devices exhibit much better hot-carrier reliability than NH3-passivated devices. The better hot-carrier reliability of N-2-passivated devices can be explained by the formation of strong Si-N bonds which are difficult to break, while effectively eliminating the weaker N-H bonds, which are inevitable in NH3-passivated devices. The results of a Fourier. transform infrared (FTIR) spectrum analysis performed in this study are consistent with this proposition.
  • Item type:Item,
    Dimensional effects on the drain current of n- and p-channel polycrystalline silicon thin film transistors
    (2000-07-01)
    Shih, PS
    ;
    Zan, HW
    ;
    Chang, TC
    ;
    Huang, TY
    ;
    Chang, CY
    N-channcl and p-channel polysilicon thin him transistors (poly-Si TFTs) with different geometries were fabricated and characterized to study the interactive effects of active channel area on drain current. We find that for both non-passivated and passivated p-TFTs, since no avalanche multiplication is involved, the drain current is increased with reduced active channel area due to the reduction of grain-boundary trap density. In contrast, a somewhat unexpected trap dependence of the kink effect is observed in n-TFTs. Consequently, the dependence of active channel area on drain current differs between non-passivated n-TFTs with large trap density and passivated n-TFTs with small trap density.
  • Item type:Item,
    Characterization and reliability of lightly-doped-drain polysilicon thin-film transistors with oxide sidewall spacer formed by one-step selective liquid phase deposition
    (2000-10-01)
    Shih, PS
    ;
    Chang, TC
    ;
    Huang, TY
    ;
    Yeh, CF
    ;
    Chang, CY
    We have proposed and successfully demonstrated a novel process for fabricating a lightly doped drain (LDD) polysilicon thin-film transistor (poly-Si TFT). The oxide sidewall spacer in the new process is formed by a simple one-step selective liquid phase deposition (LPD) at 23 degreesC. In contrast with conventional methods, this new process does not require an additional photolithographic step for defining the non-self-aligned offset gate, or the deposition of an oxide layer and subsequent etch-back to form the: self-aligned sidewall spacer. Devices fabricated by the new process have a lower leakage current and a better ON/OFF current ratio, compared with non-LDD control devices. The new device also shows excellent current saturation characteristics at high bias and better has hot-carrier endurance. Since the apparatus used for LPD oxide deposition is simple and inexpensive, the new process appears to be promising for future high-performance poly-Si TFT fabrication.
  • Item type:Item,
    A W-spacer GOLD TFT with high performance and high reliability
    (2002-09-26)
    Zan, HW
    ;
    Peng, DZ
    ;
    Shih, PS
    ;
    Chang, TC
    ;
    Liu, PT
    In this paper, we successfully fabricated Gate-Overlapped Lightly-doped Drain (GOLD) polycrystalline silicon thin-film transistors (poly-Si TFTs) with selectively deposited spacers. Under appropriate deposition conditions, tungsten (W) films can be selectively deposited on poly-Si gate electrodes to form spacers without any additional etching process. Compared to the conventional poly-Si TFTs without LDD structures, our devices effectively suppress the kink effect and the punch-through phenomenon in short-channel devices. The hot-carrier reliability of our devices is also improved due to the reduced electric field on the drain side. In addition, the transconductance of our devices is compatible to that of conventional devices. This is because the W-spacer acts as a part of gate electrode to induce channel when the device is operated under ON state. (C) 2002 Elsevier Science Ltd. All rights reserved.
  • Item type:Item,
    A study of parasitic resistance effects in thin-channel polycrystalline silicon TFTs with tungsten-clad source/drain
    (2003-08-01)
    Zan, HW
    ;
    Chang, TC
    ;
    Shih, PS
    ;
    Peng, DZ
    ;
    Kuo, PY
    With selectively-deposited tungsten film grown on source/drain regions, the parasitic source/drain resistance of thin-channel polycrystalline silicon (poly-Si) thin film transistors can be greatly reduced, leading to the improvement of device driving ability. After extracting the parasitic resistance from characteristics of devices with different channel length, the influences of parasitic resistance on device performances were discussed. A physically-based equation containing the parasitic resistance effects was derived to explain the behavior of linear transconductance under high gate voltage. Good agreements were found between calculated and measured data for both the thin-channel devices with or without tungsten-clad source/drain structure.