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Ferroelectric Characterization of Hafnium-Oxide-Based Ferroelectric Memories with Remote Nitrogen Plasma Treatments
(2019-01-01)
Lee, You-Ting
;
Chen, Hsuan-Han
;
Tung, Yi-Chun
;
Shih, Bing-Yang
;
Hsiung, Szu-Yen
In this paper, we experimentally demonstrated the advantage of remote nitrogen plasma on improving interface quality of HfO2-based ferroelectric devices. The remote nitrogen plasma not only reduces leakage current of gate stack to appropriately sustain the ferroelectricity during ferroelectric domain switching, but also effectively improve the ferroelectric fatigue to enhance endurance cycling performance.
Energy-Efficient Versatile Memories With Ferroelectric Negative Capacitance by Gate-Strain Enhancement
(2017-08-01)
Chiu, Yu-Chien
;
Cheng, Chun-Hu
;
Liou, Guan-Lin
;
Chang, Chun-Yen
;
電子工程學系及電子研究所
In this brief, we reported a ferroelectric versatile memory with strained-gate engineering. The versatile memory with high-strain-gate showed a >40% improvement on ferroelectric hysteresis window, compared to low-strain case. The high compressive stress induced from high nitrogen-content TaN enhances monoclinic-to-orthorhombic phase transition to reach stronger ferrolectric polarization and lower depolarization field. The versatile memory featuring ferroelectric negative capacitance exhibited excellent transfer characteristics of the sub-60-mVdec subthreshold swing, ultralow off-state leakage of <1fA/mu m and > 108 on/off current ratio. Furthermore, the ferroelectric versatile memory can be switched by +/- 5 V under 20-ns speed for a long endurance cycling (similar to 10(12) cycles). The low-power operation can be ascribed to the amplification of the surface potential to reach the strong inversion and fast domain polarization at the correspondingly low program/erase voltages.
Impact of Nanoscale Polarization Relaxation on Endurance Reliability of One-Transistor Hybrid Memory Using Combined Storage Mechanisms
(2015)
Chiu, Yu-Chien
;
Chang, Chun-Yen
;
Hsu, Hsiao-Hsuan
;
Cheng, Chun-Hu
;
Lee, Min-Hung
We demonstrate a novel hybrid nonvolatile memory integrated with a charge trapping mechanism and a ferroelectric polarization effect. The hybrid memory features a large threshold voltage window of 2V, fast 20-ns program/erase time, tight switching margin, and long 10(12)-cycling endurance at 85 degrees C. Such excellent endurance reliability at 85 degrees C can be ascribed to the introduction of charge-trapping node into the design of memory structure that not only weakens temperature-dependent polarization relaxation, but also improves high-temperature endurance reliability.
On the Variability of Threshold Voltage Window in Gate-Injection Versatile Memories with Sub-60mV/dec Subthreshold Swing and 10(12)-Cycling Endurance
(2016)
Chiu, Yu-Chien
;
Chang, Chun-Yen
;
Yen, Shiang-Shiou
;
Fan, Chia-Chi
;
Hsu, Hsiao-Hsuan
Incorporating a charge-trapped ZrSiO with ferroelectric HfZrO dielectrics, we demonstrated a gate-injection versatile memory with sub-60mV/dec subthreshold swing (SS) and large threshold voltage window (Delta V-T) of >2V under a fast 20-ns speed. Moreover, it is revealed that the local defects at ZrSiO/HfZrO interface affect the ferroelectric negative capacitance tuning and thus increases the variability of V-T and SS during 10(12) cycling endurance.
A novel nanowire channel poly-Si TFT functioning as transistor and nonvolatile SONOS memory
(2007-09-01)
Chen, Shih-Ching
;
Chang, Ting-Chang
;
Liu, Po-Tsun
;
Wu, Yung-Chun
;
Lin, Po-Shun
In this letter, a polycrystalline silicon thin-film transistor consisting of silicon-oxide-nitride-oxide-silicon (SONOS) stack gate dielectric and nanowire (NW) channels was investigated for the applications of transistor and nonvolatile memory. The proposed device, which is named as NW SONOS-TFT, has superior electrical characteristics of transistor, including a higher drain current, a smaller threshold voltage (V-th), and a steeper subthreshold slope. Moreover, the NW SONOS-TFT also can exhibit high program/erase efficiency under adequate bias operation. The duality of both transistor and memory device for the NW SONOS-TFT can be attributed to the trigate structure and channel corner effect.
Formation of germanium nanocrystals by rapid thermal oxidizing SiGeO layer for nonvolatile memory application
(2007-12-15)
Chen, Wei-Ren
;
Chang, Ting-Chang
;
Liu, Po-Tsun
;
Tu, Chun-Hao
;
Yeh, Jui-Lung
A new method to fabricate Ge nanocrystals by rapid thermal oxidizing SiGeO layer for nonvolatile memory application was investigated in this study. The oxidation process nucleated the Ge nanocrystals embedded in the dielectric layer was clearly observed by transmission electron microscope analysis. Moreover, an over-oxidation phenomenon for the formation of GeO2 in this work was found at higher temperature oxidation according to the X-ray photoelectron spectroscopy analysis. The obvious memory window was found in the capacitance-voltage hysteresis curve, and the program efficiency of holes was superior to electrons due to the electronic affinity of GeO2 smaller than silicon substrate for a structure of Ge nanocrystals surrounded with GeO2 layer. Furthermore, the Ge nanocrystals surrounded with GeO2 layer structure has good retention time and endurance. (c) 2007 Elsevier B.V All rights reserved.
Fort-nation of stacked nickel-silicide nanocrystals by using a co-mixed target for nonvolatile memory application
(2007-12-15)
Chen, Wei-Ren
;
Chang, Ting-Chang
;
Liu, Po-Tsun
;
Tu, Chun-Hao
;
Chi, Feng-Weng
The formation of stacked nickel-silicide nanocrystals by using a co-mixed target is proposed in this paper. High resolution transmission electron microscope analysis clearly shows the stacked nanocrystals embedded in the silicon oxide after rapid thermal oxidation. The obvious memory window can be used to define "1" and "0" states at low voltage operation. In addition, the program/erase characteristics have different charge/discharge efficiency due to the effect of stacked structure. Furthermore, good endurance and retention characteristics are exhibited for nonvolatile memory application. Besides, this technology is suitable for the fabrication of current nonvolatile memory and application of low power device. (C) 2007 Elsevier B.V. All rights reserved.
Characteristics of poly-Si TFT combined with nonvolatile SONOS memory and nanowire channels structure
(2007-12-15)
Chen, Shih-Ching
;
Chang, Ting-Chang
;
Liu, Po-Tsun
;
Wu, Yung-Chun
;
Lin, Po-Shun
In this work, we study a polycrystalline silicon thin-film transistor (poly-Si TFT) combined with a silicon-oxide-nitride-oxide-silicon (SONOS) stack gate dielectric and nanowire channels structure for the applications of transistor and nonvolatile memory. The proposed device named with NW SONOS-TFT has superior electrical characteristics of transistor and also can exhibit high program/erase (P/E) efficiency under adequate bias operation. The V-th decreases from 2.45 V to 1.76 V and subthreshold swing reduces from 0.57 V/decade to 0.42 V/decade. The programming V-th shift is improved from 2.2 V to 3.3 V at 14 V for 1 s and the erasing V-th shift is improved from -0.3 V to -1.3 V at -14 V for 1 s. The dramatic improvement can be attributed to the tri-gate structure and corner effect. In addition, the memory device has a promising data retention behavior at 85 degrees C and a 0.8 V memory window after 5 x 10(3) P/E cycles operations. Hence, the NW SONOS-TFT is suitable for application in the future system-on-panel display. (C) 2007 Elsevier B.V. All rights reserved.

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