🏛️國立陽明交通大學機構典藏

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Transparent planar indium tin oxide for a thermo-photovoltaic selective emitter
(2020-09-01)
Chen, Yu-Bin
;
Parashar, Parag
;
Yang, Yi-Hua
;
Rawat, Tejender Singh
;
Chen, Shih-Wei
Designing an efficient emitter design is an important step for achieving a highly efficient TPV conversion process. Wavelength-selective emissivity, spectra match between the emitter and TPV cells, and high thermal stability are three main characteristics that must be considered before implementing the emitter. In this work, an indium tin oxide (ITO)/sapphire emitter structure is investigated for TPV application over the temperature range from 200 degrees C to 1000 degrees C. A 1-mu m-thick ITO layer is deposited on a 650-mu m-thick sapphire substrate. In addition, 50-nm-thick SiO2 is deposited on top of the ITO to enhance the performance of emitter at high temperatures. High-temperature emissivity and absorptivity measurement of the emitter samples are obtained using FTIR and a Hitachi U-4100 spectrophotometer, respectively. The resultant SiO2/ITO/sapphire/stainless-steel planar emitter structure has selective emission with high emissivity of similar to 0.8 in the 1-1.6 mu m wavelength regime at 1000 degrees C. This emission range lies at the bandgap edge of silicon TPV cells and thus can be used to harness the true potential for making a low-cost thermophotovoltaic system. (C) 2020 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
Monolithic 3D BEOL FinFET switch arrays using location-controlled-grain technique in voltage regulator with better FOM than 2D regulators
(2019-01-01)
Hsieh, Ping-Yi
;
Chang, Yi-Jui
;
Chen, Pin-Jun
;
Chen, Chun-Liang
;
Yang, Chih-Chao
Monolithic 3D back-end of line (BEOL) FinFET switch arrays are demonstrated in large single crystalline Si islands (2.56 mu m(2)), whose location, size and shape are determined by design. Details of the improved location-controlled-grain (LCG) technique are presented. A voltage regulator implemented with the BEOL switch arrays using external control signals shows better theoretical figure of merit (FOM) of 0.089ns than 2D voltage regulators of 0.43ns.
A Low-Cost Broadband Bondwire Interconnect for Heterogeneous System Integration
(2013)
Li, Chun-Hsing
;
Ko, Chun-Lin
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Kuo, Chien-Nan
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Kuo, Ming-Ching
;
Chang, Da-Chiang
A low-cost broadband interconnect, composed of bondwires and transmission lines, is proposed for heterogeneous system integration. By designing the length and the characteristic impedance of the transmission lines, the bondwire effect can be reduced to provide an interconnect with good return loss and low insertion loss. In this work, the chip and the carrier are realized in 90-nm CMOS and GIPD process, respectively. Measured results show that the return loss and the insertion loss are better than 10 dB and 1.1 dB, respectively, from DC to 45.2 GHz.
A 8-mW 77-GHz Band CMOS LNA by Using Reduced Simultaneous Noise and Impedance Matching Technique
(2015)
Ko, Chun-Lin
;
Li, Chun-Hsing
;
Kuo, Chien-Nan
;
Kuo, Ming-Ching
;
Chang, Da-Chiang
This paper presents analysis and design of source inductance for multistage LNA at 77-GHz band in 90 nm CMOS technology. Instead of simultaneous noise and impedance matching, the analysis shows the optimum degeneration of the single stage design for millimeter-wave frequencies. A low-power 77-GHz band LNA has been demonstrated to verify the optimization result. By using the proposed method, the LNA exhibited a low noise figure of 5.1 dB and a gain of 18.1 dB at 78.5 GHz with only 8 mW from a 1-V power supply.
A 37.5-mW 8-dBm-EIRP 15.5 degrees-HPBW 338-GHz Terahertz Transmitter Using SoP Heterogeneous System Integration
(2015-02-01)
Li, Chun-Hsing
;
Chao, Tzu-Yuan
;
Lai, Chih-Wei
;
Chen, Wei-Cheng
;
Ko, Chun-Lin
A low-cost terahertz transmitter is proposed by using system-on-package (SoP) heterogeneous system integration. A signal source in 40-nm CMOS is integrated with an antenna array on a Benzocyclobutene carrier through a broadband low-loss terahertz interconnect. The signal source adopting triple-push oscillator topology is able to produce a differential output without any additional balun circuit. Hence, the power consumption and the chip area can be reduced. The antenna array containing 50 patch antennas is differentially excited to give simulated directivity, efficiency, and antenna gain as high as 22.6 dB, 88%, and 22 dBi, respectively, at 335 GHz. The terahertz interconnect employs a resonator coupling technique to provide low-loss and broadband performance while occupying a small area. Measured results show that the proposed terahertz transmitter can work at 338.4 GHz with equivalent isotropically radiated power (EIRP) of 8.0 dBm while consuming only 37.5 mW from a 1-V supply. The measured half-power beam-width can be as narrow as 15.5 degrees. The EIRP can be further raised to 9.5 dBm as the supply V-DD is increased to 1.3 V. The CMOS chip only occupies an area as small as 0.028 mm(2). All of the design efforts enable the proposed terahertz transmitter to feature in small form factor, low power dissipation, low cost, and high performance. To the best of the authors\' knowledge, this is the most compact, lowest power, lowest cost, and high-performance SoP-based terahertz transmitter reported thus far.

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🏛️國立陽明交通大學機構典藏

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