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Study of Charge Trapping Effects on AlGaN/GaN HEMTs Under UV Illumination With Pulsed I-V Measurement
(2020-06-01)
Nagarajan, Venkatesan
;
Chen, Kun-Ming
;
Chen, Bo-Yuan
;
Huang, Guo-Wei
;
Chuang, Chia-Wei
The charge trapping effects on AlGaN/GaN HEMTs under UV illumination are investigated using the pulsed current-voltage (I-V) measurement method. The test samples are unpassivated Schottky-gate HEMTs and metal-insulator-semiconductor HEMTs (MIS-HEMTs) with SiN gate dielectric. For HEMTs, the dominant charge trapping sources are the surface trap states, whereas, for MIS-HEMTs, they are trap states in the SiN gate dielectric and GaN buffer. When these devices are shined with the UV light, the drain current increases apparently in both samples owing to the generated photocurrent. By combining the UV illumination and pulsed I-V measurement, we find out the UV light has less effect on the surface charge trapping in the unpassivated HEMTs. Moreover, in MIS-HEMTs, we observe the charge trapping in the SiN gate dielectric becomes more serious under UV illumination, whereas the charge trapping in the GaN buffer is suppressed significantly. These findings are important for designing a GaN-based HEMT for photonic applications. In addition, the different responses of the surface-, buffer-, and gate-dielectric-related charge trapping to the UV light suggest that it would be easier to distinguish the trap types by introducing the UV illumination during the pulse measurement.
Low-Frequency Noise Characterization of AlGaN & x002F;GaN HEMTs and MIS-HEMTs Under UV Illumination
(2020-01-01)
Nagarajan, Venkatesan
;
Chen, Kun-Ming
;
Lin, Hsin-Yi
;
Hu, Hsin-Hui
;
Huang, Guo-Wei
The low-frequency noise characteristics of AlGaN & x002F;GaN HEMTs and MIS-HEMTs are investigated in the dark condition and under UV illumination. The test devices with a 3-& x03BC;m-thick GaN buffer and a 25-nm-thick Al_0.22Ga_0.78N barrier layer were fabricated on the silicon wafer. For MIS-HEMTs, a 25-nm-thick SiN layer was deposited as a gate dielectric. The measured low-frequency noises show a 1 & x002F;f spectrum and can be described by the carrier number fluctuation model. Different noise responses to the UV light between HEMTs and MIS-HEMTs were observed. By comparing the noise data in dark and under UV illumination, the noise sources under the gate and in the ungated gate-drain access region have been identified. From these results, we can find a design guideline to improve the noise and reliability of GaN-based devices for optoelectronic applications.
A simple extraction method for parasitic series resistances in GaN HEMTs considering non-quasi-static effects
(2019-05-01)
Nagarajan, Venkatesan
;
Chen, Kun-Ming
;
Wang, Huan-Chung
;
Singh, Sankalp Kumar
;
Anandan, Deepak
A simple technique for extracting the bias-dependent parasitic series resistances of the GaN-based high electron mobility transistor (HEMT) is demonstrated in this paper. With considering the non-quasi-static effect in devices, new analytical Z-parameter formulations are derived to determine parasitic resistances using the curve-fitting algorithm. More accuracy parasitic resistances can be obtained over a wide fitting frequency range compared to the conventional method which ignores the non-quasi-static effect. Here the intrinsic parameters are then calculated directly from intrinsic Y-parameters after de-embedding the parasitic elements in the small-signal equivalent circuit. An excellent agreement between the measured and simulated S-parameters from 100 MHz to 40 GHz is achieved, which validates the feasibility of our method for extracting the bias-dependent parasitic resistances.
Gate Recessed Quasi-Normally OFF Al2O3/AlGaN/GaN MIS-HEMT With Low Threshold Voltage Hysteresis Using PEALD AlN Interfacial Passivation Layer
(2014-07-01)
Hsieh, Ting-En
;
Chang, Edward Yi
;
Song, Yi-Zuo
;
Lin, Yueh-Chin
;
Wang, Huan-Chung
In this letter, a gate recessed normally OFF AlGaN/GaN MIS-HEMT with low threshold voltage hysteresis using Al2O3/AlN stack gate insulator is presented. The trapping effect of Al2O3/GaN interface was effectively reduced with the insertion of 2-nm AlN thin interfacial passivation layer grown by plasma enhanced atomic layer deposition. The device exhibits a threshold voltage of +1.5 V, with current density of 420 mA/mm, an OFF-state breakdown voltage of 600 V, and high ON/OFF drain current ratio of similar to 10(9).
A versatile low-resistance ohmic contact process with ohmic recess and low-temperature annealing for GaN HEMTs
(2018-09-01)
Lin, Yen-Ku
;
Bergsten, Johan
;
Leong, Hector
;
Malmros, Anna
;
Chen, Jr-Tai
Deeply recessed ohmic contacts for GaN-based high electron mobility transistors (HEMTs) are demonstrated. It is shown that low-resistance ohmic contacts can be achieved with recessing beyond the AlGaN Schottky barrier where the ohmic contacts are formed on the sidewall of the recess. This makes the process versatile and relatively insensitive to the exact recess depth. The ohmic contact is based on a gold-free metallization scheme consisting of a Ta/Al/Ta metal stack requiring a low-temperature annealing. Important parameters for this type of ohmic contact process include the metal coverage, slope of the etched sidewall, bottom Ta-layer thickness, as well as annealing temperature and duration. The optimized contact resistance is as low as 0.24 Omega mm after annealing at 575 degrees C. Moreover, this sidewall contact approach was successfully implemented on different epitaxial heterostructures with different AlGaN barrier thickness as well as with and without AlN exclusion layer. All the samples exhibited excellent contact resistances in a wide range of recess depths. The Ta-based, sidewall ohmic contact process is a promising method for forming an ohmic contact on a wide range of GaN HEMT epitaxial designs.
Enhancement-Mode GaN MIS-HEMTs With LaHfOx Gate Insulator for Power Application
(2017-08-01)
Lin, Yueh Chin
;
Huang, Yu Xiang
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Huang, Gung Ning
;
Wu, Chia Hsun
;
Yao, Jing Neng
This letter reports an E-mode GaN MIS-HEMT using a composite La2O3/HfO2 gate insulator for power device applications. The composite dielectric formed an amorphous LaHfOx layer after post-deposition annealing. The GaN MIS-HEMT with amorphous LaHfOx gate dielectric showed good oxide film quality and excellent HfLaOx/GaN interface properties, as demonstrated by the measured C-V characteristics. Consequently, the E-mode MIS-HEMT was determined to show good V-th stability with only a slight increase in the dynamic R-on after high drain bias stress.
High-Performance GaN MOSHEMTs Fabricated With ALD Al2O3 Dielectric and NBE Gate Recess Technology for High Frequency Power Applications
(2017-06-01)
Lin, Yen-Ku
;
Noda, Shuichi
;
Huang, Chia-Ching
;
Lo, Hsiao-Chieh
;
Wu, Chia-Hsun
High-performance GaN metal-oxidesemi-conductor high-electron-mobility transistors (MOSHEMTs) using Al2O3 gate dielectric deposited by atomic layer deposition (ALD) and damage-free neutral beam etch (NBE) gate recess process for millimeter-wave power applications are demonstrated. The high-quality ALD Al2O3 reduces the gate leakage current of the device and the NBE method eliminates the plasma-induced defects in the nitride materials. The MOSHEMT device fabricated exhibits a high maximum drain current density (I-DS,I-max ) of 1.65 A/mm and a high peak extrinsic transconductance (g(m.ext) ) of 653 mS/mm. The MOSHEMT device also demonstrates excellent RF performances, including f(T)/f(MAX) = 183/191 GHz, NFmin = 2.56 dB with G(AS) = 5.61 dB at 54 GHz, and an output power density of 2.7 W/mm associated with a power-added efficiency of 20.9% and a linear power gain of 9.4 dB at 38 GHz. To the best of our knowledge, the noise performance at 54 GHz is the best reported so far for the AlGaN/GaN HEMTs.
The effects of Growth Parameters on the Electrical Properties in InAlN/AlN/GaN High-Electron-Mobility Transistors (HEMTs)
(2014-01-01)
Huang, Wei-Ching
;
Wong, Yuen-Yee
;
Liu, Kuan-Shin
;
Hsieh, Chi-Feng
;
Chang, Edward Yi
The electrical properties in the InAlN/AlN/GaN high electron mobility transistor grown by metal-organic vapor deposition (MOCVD) with different growth parameters were investigated in this study. We observed that two-dimensional electron gas (2DEG) channel was influenced by thickness of AlN spacer layer and a stable stage prior to the growth of AlN spacer layer. The TEM images showed the generation of dislocations at interface between AlN/GaN and InAlN/AlN with the thicker AlN spacer layer. These dislocations acted as electron scattering center and degraded the electron mobility in the 2DEG channel. Besides, a too long stable stage also appeared degradation in the electron mobility due to the etching effect of H-2 gas. By optimizing growth parameters, the highest electron mobility of 890 cm(2)/V.s
Effect of Multiple AlN Layers on Quality of GaN Films Grown on Si Substrates
(2014-11-01)
Binh Tinh Tran
;
Lin, Kung-Liang
;
Sahoo, Kartika Chandra
;
Chung, Chen-Chen
;
Chi-Lang Nguyen
In this paper, we present the effect of multiple thin high-low-high-temperature AlN (HLHT AlN) nucleation layers on GaN film quality. A 1.9-mu m-thick GaN film gown on Si (111) substrate shows that the multiple HLHT AlN nucleation layers have a significant effect on GaN film quality. This process also plays a very important role in the growth of GaN films on Si (111) substrates. A high quality GaN film with a uniformly faceted surface with very low dislocation densities is obtained at the optimized multiple HLHT AlN nucleation layers 50-nm thick at a temperature of 1010-800-1010 degrees C and a growth pressure of 50 Torr.
Gate Recessed Quasi-Normally OFF Al2O3/AlGaN/GaN MIS-HEMT With Low Threshold Voltage Hysteresis Using PEALD AlN Interfacial Passivation Layer
(2014-07-01)
Hsieh, Ting-En
;
Chang, Edward Yi
;
Song, Yi-Zuo
;
Lin, Yueh-Chin
;
Wang, Huan-Chung
In this letter, a gate recessed normally OFF AlGaN/GaN MIS-HEMT with low threshold voltage hysteresis using Al2O3/AlN stack gate insulator is presented. The trapping effect of Al2O3/GaN interface was effectively reduced with the insertion of 2-nm AlN thin interfacial passivation layer grown by plasma enhanced atomic layer deposition. The device exhibits a threshold voltage of +1.5 V, with current density of 420 mA/mm, an OFF-state breakdown voltage of 600 V, and high ON/OFF drain current ratio of similar to 10(9).

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