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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Chang, Ting-ChangSubject: search.filters.subject.Reliability

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Now showing 1 - 4 of 4
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    Interface Defect Shielding of Electron Trapping in a-InGaZnO Thin Film Transistors
    (2020-09-01)
    Lin, Chih-Chih
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    Tai, Mao-Chou
    ;
    Chang, Ting-Chang
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    Tsao, Yu-Ching
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    Wang, Yu-Xuan
    In this work, an abnormal lowering of subthreshold swing (SS) after self-heating stress in a device with thick channel is observed. A model of interface defect shielding is proposed, based on electron trapping at the channel/gate insulator interface. The phenomenon is discussed systematically through the band diagram and extractions of the field effective mobility. Results suggest that a depletion region appears after electron trapping at the front channel, which then prevents the carriers from reaching the interface defects. Therefore, an abnormal superior electrical performance after stress is observed. Finally, a dual gate amorphous InGaZnO (a-IGZO) thin film transistor (TFT) is used to clarify the phenomenon. Results from different top gate bias voltage confirms the bulk accumulation and better gate control.
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    Effect of ELA Energy Density on Self-Heating Stress in Low-Temperature Polycrystalline Silicon Thin-Film Transistors
    (2020-08-01)
    Huang, Shin-Ping
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    Chen, Hong-Chih
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    Chen, Po-Hsun
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    Zheng, Yu-Zhe
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    Chu, Ann-Kuo
    The extent of the poly-silicon crystalline protrusion, a result of differences in excimer laser annealing (ELA), affects the performance and reliability of thin-film transistors (TFTs). This study investigates the degradation mechanism of the low-temperature polycrystalline silicon (LTPS) TFT devices with differences in crystalline protrusion under self-heating stress (SHS). Higher ELA energy will induce higher protrusion height in the interface between the poly-silicon and gate insulator (GI). This surface morphology leads to serious charge trapping into the GI layers; in contrast, the smallest degradation after SHS can be seen in the devices with the lowest protrusion height. This indicates that the degradation is caused by the surface morphology between the poly-Si and GI interface. In addition, the COMSOL simulation results confirm that the large electric field in the GI layer appears in the rough surface morphology devices; therefore, choosing the appropriate ELA energy of the poly-Si is beneficial for the applications of the driving TFT in organic light-emitting diode (OLED) display in the manufacturing industry.
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    Investigating degradation behaviors induced by hot carriers in the etch stop layer in amorphous InGaZnO thin film transistors with different electrode materials and structures
    (2017-12-31)
    Yang, Chung-I
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    Chang, Ting-Chang
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    Chen, Bo-Wei
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    Chou, Wu-Ching
    ;
    Liao, Po-Yung
    This work investigates the hot carrier effect in via-contact type amorphous indium gallium zinc oxide thin film transistors with various source/drain materials and structures. According to previous research, the redundant drain electrode plays an important role in hot carrier stress-induced degradation, which leads to carrier-trapping in the etch stop layer between the active layer and the redundant drain electrode. Hot carrier stress has different influences on device characteristics, depending on materials and structure. Hot carrier stress causes more electron trapping in the etch stop layer below the redundant drain electrode in the presence of smaller source/drain metal work function or a longer redundant drain electrode. To further verify the mechanisms of the degradation behavior, the barrier height for Fowler-Nordheim-tunneling is extracted by a fitting charge trapping model. It is found that the barrier height for Fowler-Nordheim-tunneling is different for different source/drain materials.
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    Reliability Study on Tri-Gate Nanowires Poly-Si TFTs under DC and AC Hot-Carrier Stress
    (2007)
    Wu, Yung-Chun
    ;
    Chen, Hung-Bin
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    Feng, Li-Wei
    ;
    Chang, Ting-Chang
    ;
    Liu, Po-Tsun
    This work studies reliability after dc and ac hot-carrier stress of polysilicon thin-film transistors (poly-Si TFTs) with single-channel and ten-nanowire channels, respectively. For single-channel (S1) poly-Si TFT, the device characteristics degradation under ac hot-carrier stress is severer than dc stress. In addition, the V-th and SS variation increases with the frequency increasing from 1 K Hz to 1 MHz. On the contrary, for tennanowire channels (M10) tri-gate poly-Si TFT, the V-th and SS variation is much lower than the S1 TFT with different stressing frequency. These results indicate that the M10 TFT has less deep state generation after dc and ac stress. Because the M10 TFT has more effective NH3 plasma passivation than that of S1 TFT due to the ten split nanowire channels has wide NH3 plasma passivation area. Moreover, M10 TFT has robust tri-gate control can reduce the lateral electrical field and its penetration from the drain to reduce hot-carrier effect. In ac stress study, the device degradation is dependent on the pulse failing time rather than rising time. In temperature study, the device degradation is improved as the operation temperature increasing from 25 degrees C to 75 degrees C.