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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Chang, Yuan-MingSubject: search.filters.subject.low-frequency noise

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    A Triode Device with a Gate Controllable Schottky Barrier: Germanium Nanowire Transistors and Their Applications
    (1970-01-01)
    Lin, Che-Yi
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    Chen, Chao-Fu
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    Chang, Yuan-Ming
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    Yang, Shih-Hsien
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    Lee, Ko-Chun
    Electrical contacts often dominate charge transport properties at the nanoscale because of considerable differences in nanoelectronic device interfaces arising from unique geometric and electrostatic features. Transistors with a tunable Schottky barrier between the metal and semiconductor interface might simplify circuit design. Here, germanium nanowire (Ge NW) transistors with Cu3Ge as source/drain contacts formed by both buffered oxide etching treatments and rapid thermal annealing are reported. The transistors based on this Cu3Ge/Ge/Cu3Ge heterostructure show ambipolar transistor behavior with a large on/off current ratio of more than 10(5) and 10(3) for the hole and electron regimes at room temperature, respectively. Investigations of temperature-dependent transport properties and low-frequency current fluctuations reveal that the tunable effective Schottky barriers of the Ge NW transistors accounted for the ambipolar behaviors. It is further shown that this ambipolarity can be used to realize binary-signal and data-storage functions, which greatly simplify circuit design compared with conventional technologies.
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    High Mobilities in Layered InSe Transistors with Indium-Encapsulation-Induced Surface Charge Doping
    (2018-11-02)
    Li, Mengjiao
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    Lin, Che-Yi
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    Yang, Shih-Hsien
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    Chang, Yuan-Ming
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    Chang, Jen-Kuei
    Tunability and stability in the electrical properties of 2D semiconductors pave the way for their practical applications in logic devices. A robust layered indium selenide (InSe) field-effect transistor (FET) with superior controlled stability is demonstrated by depositing an indium (In) doping layer. The optimized InSe FETs deliver an unprecedented high electron mobility up to 3700 cm(2) V-1 s(-1) at room temperature, which can be retained with 60% after 1 month. Further insight into the evolution of the position of the Fermi level and the microscopic device structure with different In thicknesses demonstrates an enhanced electron-doping behavior at the In/InSe interface. Furthermore, the contact resistance is also improved through the In insertion between InSe and Au electrodes, which coincides with the analysis of the low-frequency noise. The carrier fluctuation is attributed to the dominance of the phonon scattering events, which agrees with the observation of the temperature-dependent mobility. Finally, the flexible functionalities of the logic-circuit applications, for instance, inverter and not-and (NAND)/not-or (NOR) gates, are determined with these surface-doping InSe FETs, which establish a paradigm for 2D-based materials to overcome the bottleneck in the development of electronic devices.
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    The impact of electrical contacts and contact-induced ultralow noise amplitudes in layered transistors
    (2016-12)
    Hsu, Chih-Kai
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    Lin, Chi-Yi
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    Li, Wenwu
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    Sun, Huabin
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    Xu, Yong
    Electrical contacts made of conducting channels with external circuitry significantly impact electronic performances, in particular for two-dimensional semiconductors. This work presents a systematic study of back-to-back Schottky contacts to a layered compound of semiconducting flakes through static and dynamic electrical measurements and the first demonstration of Schottky barrier-dominated, p-type PbSnS2 field-effect transistors. In the static analysis, the Schottky barrier height of the layered transistors can be modulated by applied electrostatic fields, while the contact-dominated fluctuations render to the 1/f electric noise and induce a normalized noise amplitude in the order of 10(-9)-10(-8). Such an ultralow-noise amplitude, which is never observed in other layered semiconducting transistors, is ascribed to the existence of Schottky barriers. Our experimental results provide a nuanced perspective for advancing the understanding of performance limit with increasing numbers of layers for electronic development.