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    Simultaneous quality improvement of tunneling- and interpoly-oxides of nonvolatile memory devices by NH3 and N2O nitridation
    (2003-01-01)
    Chao, TS
    ;
    Chang, TH
    ;
    電子物理學系
    ;
    Department of Electrophysics
    In this paper, we found the nitridation on the interpoly-oxide with NH3 and N2O processes can simultaneously improve the quality of both tunneling oxide and interpoly-oxide. Three types of poly-Si for floating gate are investigated. We found in-situ doped poly -Si shows the best performance in terms of breakdown filed, charge to breakdown (Q(BD)) and trapping rate The Q(BD) of interpoly-oxide can be reached as high as 35 C/cm(2). This scheme is very promising for nonvolatile memory devices.
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    Suppression of boron penetration in BF2+-implanted poly-Si gate
    (1996-12-01)
    Chao, TS
    ;
    Chu, CH
    ;
    Wang, CF
    ;
    Ho, KJ
    ;
    Lei, TF
    In this paper, a comprehensive study of gate engineering to suppress the penetration of boron in p-type metaloxide-semiconductor held-effect transistor (MOSFET) with the p(+)-poly-Si-gate is reported. Four types of poly-Si gate structure, two types of gate dielectrics were investigated to suppress the boron penetration. Among the different gate structures, the stacked amorphous silicon structure was found to be the most effective way to retard the boron penetration. N2O oxide exhibited a better retarding of the boron diffusion as compared with the O-2 oxide. It was found that a combination of stacked amorphous silicon with N2O oxide is the most effective way to suppress the boron penetration. Thermal stability, oxide integrity, and D-it of this sample are superior to all the other samples.
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    Mobility enhancement in local strain channel nMOSFETs by stacked a-Si/poly-Si gate and capping nitride
    (2005-04-01)
    Lu, TY
    ;
    Chao, TS
    ;
    交大名義發表
    ;
    National Chiao Tung University
    A local strained channel nMOSFET has been fabricated by a stress control technique utilizing a stacked a-Si/poly-Si gate and a SiN capping layer. It is found that the transconductance (G(M)) of nMOSFETs increases as the thickness of a-Si is increased. We also found that the G(M) of devices with the SiN capping layer exhibits a 17% increase compared to that of its counterparts. The stacked gate a-Si/poly-Si with the capping layer can improve the G(M) further to 29% more than the single-poly-Si gate structure without SiN capping layer.
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    Improvement of reliability of metal-oxide semiconductor field-effect transistors with N2O nitrided gate oxide and N2O polysilicon gate reoxidation
    (1998-10-01)
    Lai, CS
    ;
    Chao, TS
    ;
    Lei, TF
    ;
    Lee, CL
    ;
    Huang, TY
    A systematic study of the impact of the reliability of metal-oxide semiconductor field-effect transistors (MOSFETs) with N2O nitrided gate oxides and N2O poly-reoxidation was conducted. The improvements include hot carrier immunity, suppression of reverse short channel effect and suppression of plasma-induced degradation. These improvements are due to nitrogen incorporation at the oxide/Si-substrate interface. All data presented in this study involve substantially low thermal budget (850 degrees C), making this N2O-related technology extremely attractive and promising for future scaled devices.
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    A study on the radiation hardness of flash cell with horn-shaped floating-gate
    (1997-09-01)
    Huang, TY
    ;
    Jong, FC
    ;
    Chao, TS
    ;
    Lin, HC
    ;
    Leu, LY
    The effects of radiation on the characteristics of split-gate electrical erasable programmable read only memory (EEPROM)/flash cells with recently-proposed horn-shaped floating gates are studied in terms of cell read current; data retention, cycling endurance, program/erase efficiency, threshold voltage and junction leakage. Our results show that the cells appear to survive after 1 Mrad (Si) Co-60 irradiation. Moreover, the after-irradiation cell read current actually increases in the ''erase'' (i.e., low-threshold voltage, high-conducting) state (i.e., improves), albeit the cell read current also increases in the ''program'' (i.e., high-threshold voltage, low-conducting) state (i.e., a degradation). Our results also show that, despite an improvement in the initial read current in the ''erase'' state immediately after radiation, the write/erase cycling endurance of the flash cells is significantly impeded after irradiation, due to a much faster ''window closure'' rate in the ''erase'' state, although the cell read current is found to remain relatively stable in the ''program'' state after cycling.
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    Physical and electrical characterization of ZrO2 gate insulators deposited on Si(100) using Zr(O-i-Pr)(2)(thd)(2) and O-2
    (2002-06-01)
    Chen, HW
    ;
    Huang, TY
    ;
    Landheer, D
    ;
    Wu, X
    ;
    Moisa, S
    The characteristics of ultrathin ZrO2 films deposited using molecular oxygen and the zirconium precursor Zr(O-i-Pr)(2)(thd)(2) [where O-i-Pr is isopropoxide and thd is 2,2,6,6-tetramethyl-3,5-heptanedionate] were investigated. The organometallic was dissolved as a 0.15 M solution in octane and introduced into the deposition chamber using a liquid injection system. The deposition rate was insensitive to molecular oxygen flow but changed with liquid injection rate and was thermally activated in the range 390-550degreesC. No evidence of Zr-C and Zr-Si bonds were found in the X-ray photoelectron spectroscopy (XPS), spectra, and carbon concentrations, 0.1 atom %, the detection limit of the XPS depth profiling measurements, were obtained at the lowest deposition temperatures and deposition rates. High-resolution transmission electron microscopy showed the ZrO2 films to be polycrystalline as deposited, with an amorphous zirconium silicate interfacial layer. The effects of postdeposition annealing were also demonstrated. After proper annealing treatments, promising capacitance-voltage and current-voltage characteristics were achieved. A film with an equivalent oxide thickness of 2.3 nm showed current reductions of approximately two orders of magnitude when compared to SiO2, but some improvements are required if these films are to be used as a gate-insulator beyond the 100 nm CMOS (complementary metal oxide semiconductor) technology node. (C) 2002 The Electrochemical Society.
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    Mechanism of nitrogen coimplant for suppressing boron penetration in p(+)-polycrystalline silicon gate of p metal-oxide semiconductor field effect transistor
    (1996-09-16)
    Chao, TS
    ;
    Liaw, MC
    ;
    Chu, CH
    ;
    Chang, CY
    ;
    Chien, CH
    The mechanism of the nitrogen co-implant to suppress the boron penetration in p(+)-polycrystalline silicon gate has been investigated. The nitrogen coimplant with the BF, combines with the boron to form a B-N complex which results in a retardation of boron diffusion. It is found that metal-oxide-silicon capacitors with nitrogen implantation show improved electrical properties. (C) 1996 American Institute of Physics.
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    High quality ultrathin CoTiO3 high-k gate dielectrics
    (2000-09-01)
    Pan, TM
    ;
    Lei, TF
    ;
    Chao, TS
    ;
    Chang, KL
    ;
    Hsieh, KC
    A novel high-k cobalt-titanium oxide (CoTiO3) was formed by directly oxidizing sputtered Co/Ti film. Al/CoTiO3/Si3N4/Si capacitor structure was fabricated and measured. The effective dielectric constant with buffered layer for CoTiO3 gate dielectric can reach as high as 40 while depicting excellent electrical properties at the same time. This novel metal oxide thus appears to be a promising high-k gate dielectric for future ultralarge scale integrated devices. (C) 2000 The Electrochemical Society. S1099-0062(00)03-095-9. All rights reserved.
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    Electrical characteristics of thin cerium oxide film on silicon substrate by reactive DC sputtering
    (2001-09-01)
    Pan, TM
    ;
    Chien, CH
    ;
    Lei, TF
    ;
    Chao, TS
    ;
    Huang, TY
    Electrical proper-ties of CeO2 films prepared by reactive dc sputtering on Si(100) substrate with and without the incorporation of a thin barrier layer were investigated. X-ray diffraction spectra revealed that without the thin barrier layer, single-crystal CeO2 is formed on Si(100) substrate. At an equivalent oxide thickness of 2.8 nm, CeO2 films exhibit a leakage current which is four orders of magnitude lower than that of the conventional SiO2 film at an applied bias of 2 V. Only negligible stress-induced leakage current is observed after high field stressing. The incorporation of the thin silicon nitride buffer layer, however, degraded the crystalline structure of CeO2, accompanied by deteriorated electrical properties such as leakage current and fixed charges. CeO2 film without the barrier layer is thus attractive as the high dielectric constant gate insulator for future ultralarge scale integration devices. (C) 2001 The Electrochemical Society.
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    Physical and electrical characterization of ZrO(2) gate insulators deposited on Si(100) using Zr(O(i)-Pr)(2)(thd)(2) and O(2)
    (2002-06-01)
    Chen, HW
    ;
    Huang, TY
    ;
    Landheer, D
    ;
    Wu, X
    ;
    Moisa, S
    The characteristics of ultrathin ZrO(2) films deposited using molecular oxygen and the zirconium precursor Zr(O(i)-Pr)(2)(thd)(2) [where O(i)-Pr is isopropoxide and thd is 2,2,6,6-tetramethyl-3,5-heptanedionate] were investigated. The organometallic was dissolved as a 0.15 M solution in octane and introduced into the deposition chamber using a liquid injection system. The deposition rate was insensitive to molecular oxygen flow but changed with liquid injection rate and was thermally activated in the range 390-550degreesC. No evidence of Zr-C and Zr-Si bonds were found in the X-ray photoelectron spectroscopy (XPS), spectra, and carbon concentrations, 0.1 atom %, the detection limit of the XPS depth profiling measurements, were obtained at the lowest deposition temperatures and deposition rates. High-resolution transmission electron microscopy showed the ZrO(2) films to be polycrystalline as deposited, with an amorphous zirconium silicate interfacial layer. The effects of postdeposition annealing were also demonstrated. After proper annealing treatments, promising capacitance-voltage and current-voltage characteristics were achieved. A film with an equivalent oxide thickness of 2.3 nm showed current reductions of approximately two orders of magnitude when compared to SiO(2), but some improvements are required if these films are to be used as a gate-insulator beyond the 100 nm CMOS (complementary metal oxide semiconductor) technology node. (C) 2002 The Electrochemical Society.