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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Chao, Tien-ShengSubject: search.filters.subject.strain

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Now showing 1 - 7 of 7
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    The Zero-Temperature-Coefficient Point Modeling of DTMOS in CMOS Integration
    (2010-10-01)
    Wang, Kuan-Ti
    ;
    Lin, Wan-Chyi
    ;
    Chao, Tien-Sheng
    ;
    電子物理學系
    ;
    Department of Electrophysics
    For the first time, analytical expressions of zero-temperature-coefficient (ZTC) point modeling of DTMOS transistor are successfully presented in detail. New analytical formulations for the linear and saturation regions of DTMOS transistor operation that make certain the drive current to be temperature independent for the ideal gate voltage are developed. The maximum errors of 0.87% and 2.35% in the linear and saturation regions, respectively, confirm a good agreement between our DTMOS ZTC point model and the experimental data. Compared to conventional MOSFET, the lower V(g) (ZTC) with higher overdrive current of DTMOS improves the integrated circuit speed and efficiency for the low-power-consumption concept in green CMOS technology.
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    Impacts of Multiple Strain-Gate Engineering on a Zero-Temperature-Coefficient Point
    (2013-04-01)
    Chang, Tien-Shun
    ;
    Lu, Tsung Yi
    ;
    Chao, Tien-Sheng
    ;
    交大名義發表
    ;
    National Chiao Tung University
    The impacts of zero-temperature-coefficient (ZTC) points of various strained devices is presented in this letter. The current and mobility are reduced at high temperature by phonon scattering. The degree of mobility reduction becomes severe on devices with multiple strain-gate engineering. The reduction of mobility becomes severe as a result of impurity scattering, which results from gate implantation impurities. The ZTC point is decreased by multiple strain-gate engineering due to the decreased Vth.
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    Temperature Dependence of Electron Mobility on Strained nMOSFETs Fabricated by Strain-Gate Engineering
    (2012-07-01)
    Chang, Tien-Shun
    ;
    Lu, Tsung Yi
    ;
    Chao, Tien-Sheng
    ;
    電子物理學系
    ;
    Department of Electrophysics
    An effective electron mobility improvement that uses strain-proximity-free technique (SPFT) has been demonstrated using strain-gate engineering. The electron mobility of nMOSFETs with SPFT exhibits a 15% increase over that of counterpart techniques. The preamorphous layer (PAL) gate structure on the SPFT showed a further performance boost. The electron mobility exhibits a 52% improvement in nMOSFET using a combination of SPFT and PAL gate structure. Furthermore, the gain in electron mobility in the SPFT in combination with PAL gate structure decreases at high temperatures. Gate dielectric interface states and ionized gate impurities inducing carrier scattering will play important roles when operating devices under high-temperature conditions.
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    Impacts of the Underlying Insulating Layers on the MILC Growth Length and Electrical Characteristics
    (2012-02-01)
    Liao, Chia-Chun
    ;
    Lin, Min-Chen
    ;
    Liu, Shao-Xuan
    ;
    Chao, Tien-Sheng
    ;
    電子物理學系
    This letter investigates the impacts of proximity layers on metal-induced lateral crystallization (MILC). The underlying insulating layers not only affect the MILC growth length but also influence the electrical characteristics. Based on the comparison among the underlying insulating layers, SiN is unsuitable to be an underlying insulating layer because of concerns regarding the crystallization condition. This letter proposes three reasonable mechanisms, including the gettering of Ni, intrinsic stress, and the involvement of hydrogen to enhance the understanding of the impacts of proximity layers.
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    Performance enhancement by local strain in (110) channel n-channel metal-oxide-semicondiactor field-effect transistors on (111) substrate
    (2007-09-01)
    Lo, Wen-Cheng
    ;
    Ku, Ya-Hsin
    ;
    Lee, Yao-Jen
    ;
    Chao, Tien-Sheng
    ;
    Chang, Chun-Yen
    In this study, an n-channel metal-oxide-semiconductor field-effect transistor (nMOSFET) fabricated with local strained channel techniques on a (111) Si substrate using a SiN capping layer with high mechanical stress and the stack gate of amorphous silicon (alpha-Si) and polycrystal line silicon (poly-Si) was investigated. By using these techniques, the performance improvement of the nMOSFETs in the (110) channel direction on the (111) substrate was achieved. The on-current and transconductance (G) increased with increasing SiN capping layer or alpha-Si layer thickness. Our experimental results show that devices with a 700 A a-Si layer show a 6.7% on-current improvement percentage relative to those with a 200 A. alpha-Si layer, and a corresponding G. improvement percentage of 10.2%. In addition, charge pumping current/interface state density decreased for the samples with a thicker SiN layer.
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    Characterization of Enhanced Stress Memorization Technique on nMOSFETs by Multiple Strain-Gate Engineering
    (2011-04-01)
    Lu, Tsung-Yi
    ;
    Chang, Tien-Shun
    ;
    Huang, Shih-An
    ;
    Chao, Tien-Sheng
    ;
    電子物理學系
    To extend a carrier mobility improvement by strain engineering in high-density and small-gate-space complementary metal-oxide-semiconductor (CMOS) circuits, we have proposed a new stress memorization technique (SMT) that uses a strain proximity free technique (SPFT) to demonstrate the mobility improvement through multiple strain-gate engineering. The electron mobility of n-channel metal-oxide-semiconductor (MOS) field-effect transistors with the SPFT exhibits a 14% increase over counterpart techniques. Compared with the conventional SMT, the SPFT avoids the limitation of the stressor volume for the performance improvement in high-density CMOS circuits. We also found that the preamorphous layer (PAL) gate structure in combination with the SPFT can improve the mobility further to 31% greater than standard devices. Moreover, an additional 30% mobility enhancement can be achieved by using a dynamic threshold-voltage MOS and combining the PAL gate structure with the SPFT, respectively. The gate-oxide reliability and the channel-hot-carrier reliability are also analyzed. Our results show a mobility improvement by the SPFT, a slightly increased gate leakage current, and degraded channel-hot-carrier reliability.
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    Benefit of NMOS by Compressive SiN as Stress Memorization Technique and Its Mechanism
    (2010-04-01)
    Liao, Chia-Chun
    ;
    Chiang, Tsung-Yu
    ;
    Lin, Min-Chen
    ;
    Chao, Tien-Sheng
    ;
    電子物理學系
    In this letter, we certify that the compressive SiN capping layer has more potential than the tensile layer for fabrication using the stress memorization technique to enhance NMOS mobility. The mechanism that we have proposed implies that the conventional choice of the capping layer should bemodulated from the point of view of stress shift rather than using the highest tensile film.