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Now showing 1 - 10 of 143

Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters
(2020-09-01)
Sung, Po-Jung
;
Chang, Shu-Wei
;
Kao, Kuo-Hsing
;
Wu, Chien-Ting
;
Su, Chun-Jung
In this study, conventional CMOS and complementary field-effect transistor (CFET) inverters based on a vertically stacked-nanosheet (NS) structure were fabricated. The NS below 8-nm channel layer thickness (T-Si) was obtained by dry etching and wet etching processes. The channel thickness is controlled by dry etching, and the channel width was shrunk down by wet etching. Compared to single nanowire field-effect transistors (NSFETs), stacked NSFETs exhibit higher ON-current performance. For the CMOS inverter, the voltage transfer characteristics (VTCs) could be matched much better by adjusting the channel widths and layers for N-channel MOSFET (NFET) and P-channel MOSFET (PFET), respectively. For the CFET inverter, layout areas could be reduced and requires less number of lithographic and ion implantation steps contrary to the CMOS inverter. However, we observe that the VTCs of the CFET inverters still show asymmetric behavior due to the difficulties of adjustment in NS layers and systematic behavior of threshold voltages for NFETs/PFETs. This work experimentally demonstrates the CMOS and CFET inverters on the vertically stacked NS structure, which is promising for system-on-panel (SoP) and 3-D-ICs applications.
Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter
(2020-01-01)
Sung, Po-Jung
;
Su, Chun-Jung
;
Lo, Shih-Hsuan
;
Hsueh, Fu-Kuo
;
Lu, Darsen D.
In this study, ferroelectric FETs (FeFETs) and CMOS inverters are fabricated and analyzed, exhibiting 13% of 593 devices with sub-60 mV subthreshold swing (SS) at room temperature. Forming gas annealing (FGA) is found to not only enhance ferroelectricity but also significantly improve FeFET electrostatics. The experimental results indicate that FeFET with a narrow width shows weaker ferroelectric properties, and SS of sub-60 mV/dec with I-D change less than two orders of magnitude. However, FeFET with a broad channel width reveals stronger ferroelectric properties, and SS of sub-60 mV/dec is over 2 orders of magnitude of I-d. Finally, typical voltage transfer characteristics (VTCs) of a FeFET CMOS inverter with double sweeps at various V-D from 0.6 to 2 V are demonstrated. The results show that hysteresis in a FeFET CMOS inverter could have both clockwise (CW) and counter-clockwise (CCW) loops.
Characteristics of Poly-Si Junctionless FinFETs With HfZrO Using Forming Gas Annealing
(2020-01-01)
Chung, Sheng-Ti
;
Lee, Yao-Jen
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Chao, Tien-Sheng
;
電子物理學系
;
Department of Electrophysics
In this study, an effective method was proposed to enhance the current drivability of junctionless field-effect transistors (JL-FETs) by utilizing ferroelectric effects. The ferroelectric layers were deposited on JL-FinFETs. The poly-Si junctionless FinFETs (JL-FinFETs) with HfZrO were successfully fabricated and demonstrated. The subthreshold slope (S.S.) of JL-FinFETs with HfZrO was very sensitive to post-metal annealing (PMA) conditions and fin width. With PMA at 700 & x00B0;C, steeper S.S. and I_on& x002F;I_off> 10(7) could be obtained owing to the ferroelectric effect. JL-FinFETs with PMA at 700 & x00B0;C possessed lower I_off and offered the promise of higher integration flexibility for Si CMOS compatible process for future applications. Besides, the JL-FinFETs with forming gas annealing (FGA) had a small hysteresis and achieved the improved S.S.
Nitride Induced Stress Affecting Crystallinity of Sidewall Damascene Gate-All-Around Nanowire Poly-Si FETs
(2020-01-01)
Shen, Chuan-Hui
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Chen, Wei-Yen
;
Lee, Shen-Yang
;
Ku, Po-Yi
;
Chao, Tien-Sheng
In this article, poly-Si gate-all-around (GAA) field effect transistors (FETs) using sidewall damascene method are successfully demonstrated. By manipulating the stress which is imposed by nitride layer, the crystallinity of poly-Si channels can be modified easily by changing the thickness of nitride layer. The better crystallinity of the devices with 60 & x00A0;nm top nitride is attributed to larger average grain size and fewer defects, leading to higher field-effect carrier mobility compared to 40 and 80 & x00A0;nm top nitride layer devices. Both n-type and p-type devices exhibit superior electrical characteristics including higher on-state current of 40 & x00A0;& x03BC;A & x002F;& x03BC;m (n-type) and 26 & x00A0;& x03BC;A & x002F;& x03BC;m (p-type), steep subthreshold swing of 82 & x00A0;mV & x002F;dec. (n-type) and 104 & x00A0;mV & x002F;dec. (p-type), an extremely low drain-induced barrier lowering (DIBL) of 4.6 & x00A0;mV & x002F;V (n-type) and 16.6 & x00A0;mV & x002F;V (p-type), and high I_on& x002F;I_off current ratio larger than seven orders of magnitude. The thermal stability and gate stress reliability measurement of sidewall damascene GAA nanowire poly-Si devices were also investigated. With better crystallinity, electrical characteristics of GAA nanowire poly-Si devices degrade less under same elevated temperature condition. Devices characteristics remain unchanged after long gate stress time. This simple fabrication process makes it a potential candidate for future three-dimensional integrated-circuit (3D-IC) and low-cost Internet of Things (IoTs) applications.
Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs With MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs
(2020-02-01)
Lee, Shen-Yang
;
Chen, Han-Wei
;
Shen, Chiuan-Huei
;
Kuo, Po-Yi
;
Chung, Chun-Chih
In this article, we successfully fabricated nanowire (NW) negative capacitance (NC)-related ferroelectric FETs (FE-FETs) with two structures: trigate (TG) and gate-all-around (GAA). Planar capacitors with a metal-FE-metal (MFM) structure were investigated first. Post-metal annealing (PMA) at 700 resulted in the best ferroelectricity. This condition was considerably different from that of directly stacking onto NWs because of the difference in size and curvature between planar and TG or GAA structures. Because of the addition of an underlying ZrO2 seed layer, Hf ZrxO2 in the gate-stack has been crystallized before the PMA process. In addition, two different gate-stack configurations, MFM-insulator-semiconductor (MFMIS) and metal-FE-insulator-semiconductor (MFIS), were investigated for the GAA structure. We determined that MFMIS displayed considerably more favorable subthreshold behavior and ON-state current compared with MFIS. NC-related phenomena, such as negative drain-induced barrier lowering and negative differential resistance, were observed.
Experimental Demonstration of Performance Enhancement of MFMIS and MFIS for 5-nm x 12.5-nm Poly-Si Nanowire Gate-All-Around Negative Capacitance FETs Featuring Seed-Layer and PMA-Free Process
(2019-01-01)
Lee, Shen-Yang
;
Chen, Han-Wei
;
Shen, Chiuan-Huei
;
Kuo, Po-Yi
;
Chung, Chun-Chih
We have experimentally demonstrated fully suspended nanowire ( NW) gate-all-around (GAA) negative-capacitance (NC) field-effect transistors (FETs) with ultrasmall channel dimensions (5-nm x 12.5-nm); they exhibit a remarkable I-on-I-off ratio of over 10(10). This work, for the first time, experimentally studies and compares the structures of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS) NCFETs. The GAA with the MFMIS structure has a higher on-state current owing to the metallic equal-potential layer and superior S.S.(min) of 39.22 mV/decade. A ZrO2 seed-layer is inserted under Hf Zr1-x O-x (HZO) to improve the ferroelectric crystallinity. Consequently, post-metal annealing (PMA), the conventional crystallization annealing step, can be omitted in the presence of o-phase. The gate current (I-G) is monitored to verify the multi-domain HZO. A negative DIBL of -160 mV/V is observed because of the strong NC effect corresponding to previous simulated results.
Experimental Demonstration of Stacked Gate- All-Around Poly-Si Nanowires Negative Capacitance FETs With Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process
(2019-11-01)
Lee, Shen-Yang
;
Chen, Han-Wei
;
Shen, Chiuan-Huei
;
Kuo, Po-Yi
;
Chung, Chun-Chih
For the first time, two-layer stacked nanowire gate-all-around (GAA) negative capacitance (NC) field-effect transistors (FETs) with an ultrasmall poly-Si channel that has a size of $5.3\times9$ nm(2) and a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) are experimentally demonstrated. FETs exhibit a remarkable I-on-I-off ratio of more than 10(8). We demonstrated stacked channels, double layers, GAA NC-FET with a threshold voltage ( ${V}_{\textit {TH}}$ ) of 0.61 V, and a superior subthreshold behavior with an average and minimum sub- ${V}_{\textit {TH}}$ slope of 43.85 and 26.84 mV/dec, respectively. An additional ZrO2 seed layer was inserted under the Hf $_{{1-}{x}}$ ZrxO2 layer to improve ferroelectric crystallinity. Thus, the conventional crystallization annealing step can be omitted due to the presence of the orthorhombic phase ( ${o}$ -phase) before further post-metal annealing (PMA).
Self-Limited Low-Temperature Trimming and Fully Silicided S/D for Vertically Stacked Cantilever Gate-All-Around Poly-Si Junctionless Nanosheet Transistors
(2019-01-01)
Chung, Chris Chun-Chih
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Ko, Chun-Ming
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Chao, Tien-Sheng
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電子物理學系
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Department of Electrophysics
A self-limited low-temperature trimming process is demonstrated without surface morphology degradation. It shows great potential to control the trimming process with a large process window (400900 s). Subthreshold characteristics are improved and I_off is drastically reduced (two orders of magnitude) with increasing trimming cycles. Full silicidation on the source/drain (FUSI-S/D) is performed to improve I_on. Surprisingly, after silicidation, both I_on and ${\boldsymbol{\mu }} _{\mathrm{ FE}}$ shows degradation despite that the series resistance is improved. An ultrathin body junctionless (UTB-JL) device is fabricated to investigate the degradation cause by direct CV measurement on the device, which can give us an insight into the details of the change with the silicidation.
Characteristics of In0.7Ga0.3As MOS Capacitors Obtained using Hydrochloric Acid Treatment, Ammonium Sulfide Passivation, Methanol Treatment, and Forming Gas Annealing
(2019-08-14)
Chung, Sheng-Ti
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Huang, Yi-Chin
;
Fu, Yen-Chun
;
Lee, Yao-Jen
;
Chao, Tien-Sheng
This paper proposes a chemical pre-treatment process to reduce sulfate prior to atomic layer deposition of Al2O3 gate dielectrics on n-doped In0.7Ga0.3As layers to form metal oxide semiconductor capacitors (MOSCAPs). Cleaning with methanol was done after hydrogen chloride etching and ammonium sulfide passivation. X-ray photoelectron spectroscopy performed on the sample with methanol cleaning indicated that its native oxide regrowth was effectively prevented on the sulfur-passivated In0.7Ga0.3As surface under air exposure. By analysis using atomic force microscopy of the sample cleaned using methanol, no further increase of surface roughness was observed after 5 months of air exposure. In addition, a mid-gap interface defect density (D-it) of 1.3 x 10(12) cm(-2) eV(-1) was obtained from this sample. After forming gas annealing (FGA), the D-it was improved significantly, to a value below 10(12) cm(-2) eV(-1). The obtained data indicate that the combination of chemical pre-treatment and FGA is advantageous to passivating the trap states on In0.7Ga0.3As MOSCAPs. (C) 2019 The Electrochemical Society.
X-ray photoelectron spectroscopy energy band alignment of spin-on CoTiO3 high-k dielectric prepared by sol-gel spin coating method
(2008-09-01)
Kao, Kuo-Hsing
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Chuang, Shiow-Huey
;
Wu, Woei-Cherng
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Chao, Tien-Sheng
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Chen, Jian-Hao
The characteristics of CoTiO3 high-k dielectric prepared by sol-gel spin coating method had been demonstrated. High electrical permittivity (k similar to 40.2) of CoTiO3 dielectric was extracted via the transmission electron microscopy image and capacitance-voltage curves. In addition, the valence band offset between thermal SiO2 and spin-on CoTiO3 was about 4.0 eV, which was detected by x-ray photoelectron spectroscopy. The band gaps of thermal SiO2 and spin-on CoTiO3 were 9.0 and 2.2 eV, respectively. Energy band alignment of spin-on CoTiO3 directly with SiO2 and indirectly with Si was determined in this work. (c) 2008 American Institute of Physics.

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