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Author: search.filters.author.Chen, CWSubject: search.filters.subject.copper

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    Process sensitivity and robustness analysis of via-first dual-damascene process
    (2003-05-01)
    Tsui, BY
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    Chen, CW
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    Huang, SM
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    Lin, SS
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    電子工程學系及電子研究所
    Sacrificial layer (SACL) coating had been proposed to protect the sealing layer of underlying copper lines during trench etching as via-first scheme is employed for dual-damascene patterning. Because the coated SACL thickness depends on via size and via density, the process window is hard to identify. In this paper, the criteria for a successful SACL process are derived. A four-step procedure for SACL process developing is also proposed. It is suggested that shallow trench depth and medium etch rate selectivity between inter-metal-dielectric and SACL material are preferred. The SACL thickness in via can be adjusted by adjusting the overetching percentage at the SACL breakthrough step so that the criteria are satisfied. The validity of the proposed criteria is proved by the very high yield of via chains with via size ranging from 0.27 to 0.16 mum. It is concluded that the SACL process can be robust and can be employed to reduce the thickness of the capping layer effectively even beyond the 0.13-mum technology node.
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    CMP of ultra low-k material porous-polysilazane (PPSZ) for interconnect applications
    (2004-01-30)
    Chang, TC
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    Tsai, TM
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    Liu, PT
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    Chen, CW
    ;
    Yan, ST
    In this article, we investigated the impact of chemical mechanical polishing (CMP) on an ultra low dielectric constant (ultra low-k) material Porous-Polysilazane (PPSZ) with slurries of metal polishing during interconnect manufacture process. Since the CMP processing of metals such as TaN and Cu are inevitable steps for interconnect fabrication, we have utilized two types of slurries (marked as TaN and Cu slurries) to evaluate their effects on the dielectric properties of PPSZ films. Electrical and material analyses have shown surface planarity and dielectric properties of PPSZ films will not be degraded during these metal CMP processes. This indicates that the ultra low-k PPSZ films are promising for inter-level dielectric (ILD) applications in ultra large-scale integrated circuits (ULSI) technology. (C) 2003 Elsevier B.V. All rights reserved.