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Item type:Item, How Well Can We Extract the Permanent Displacement from Low-Cost MEMS Accelerometers?(2017-11-01) ;Jan, Jyh Cherng ;Chao, Wei-An ;Wu, Yih-Min ;Chen, Chien-ChihLin, Cheng-HorngFollowing the recent establishment of a high-density seismic network equipped with low-cost micro-electro-mechanical system (MEMS) P-wave-alert-device (P-Alert) by the earthquake early warning (EEW) research group at the National Taiwan University, a large quantity of strong-motion records from moderate-magnitude earthquakes (M-L > 6) around Taiwan has been accumulated. Using a data preprocessing scheme to recover the dynamic average embedded within the P-Alert data, we adopted an automatic baseline correction approach for the P-Alert accelerograms to determine the coseismic deformation (Cd). Comparisons between the Cd values determined using global positioning system (GPS) data, strong-motion records from the P-Alert network, and data from the Taiwan Strong Motion Instrumentation Program (TSMIP) demonstrates that the near-real-time determination of Cd values (>2 cm), which provide crucial information for seismic hazard mitigation, is possible using records from low-cost MEMS accelerometers.Item type:Item, DAPs: Dynamic Adjustment and Partial Sampling for Multithreaded/Multicore Simulation(2014-01-01) ;Chen, Chien-Chih ;Peng, Yin-Chi ;Chen, Cheng-Fen ;Wu, Wei-ShanMin, QinghaoFaced with increasingly large multicore chip designs, architects need fast and accurate simulations for their exploration of design spaces within a limited simulation time budget. In multithreaded applications, threads cannot run simultaneously. Sampling is commonly used to reduce simulation time, but conventional sampling barely detects the instantaneous program variations of synchronization events and the inconsistency between phases of each core. This work proposes a dynamic adjustment and partial sampling technique (DAPs), consisting of aggressive sampling, lazy sampling, and regular sampling, to overcome thread interference in multithreaded applications. Moreover, DAPs partially selects sampling cores to reduce the overhead of sampling inconsistent phases.Item type:Item, Leveraging Data Lifetime for Energy-Aware Last Level Non-Volatile SRAM Caches using Redundant Store Elimination(2014-01-01) ;Tsai, Hsiang-Jen ;Chen, Chien-Chih ;Yang, Keng-Hao ;Yang, Ting-ChinHuang, Li-YueNVM has commonly been used to address increasingly large last-level caches (LLCs) requirements by reducing leakage. However, frequent data-writing operations result in increased energy consumption. In this context, a promising memory technology, Non-volatile SRAM (nvSRAM), enables normal and standby operation modes which can be used to store various types of data. However, nvSRAM suffers from high dynamic energy usage due to frequent switching between operation modes. In this paper, we propose a redundant store elimination (RSE) scheme which, on average, discards 94% of needless bit-write operations. Moreover, we present a retention-aware cache management policy to reduce data updates of cache blocks, based on the correlation between data lifetime and cache types. Experimental results demonstrate that our proposal can improve energy consumption of SRAM-based and RRAM-based LLCs by 57% and 31%, respectively.Item type:Item, Logistic regression model for predicting the failure probability of a landslide dam(2011-01-10) ;Dong, Jia-Jyun ;Tung, Yu-Hsiang ;Chen, Chien-Chih ;Liao, Jyh-JongPan, Yii-WenLandslides may obstruct river flow and result in landslide dams; they occur in many regions of the world. The formation and disappearance of natural lakes involve a complex earth-surface process. According to the lessons learned from many historical cases, landslide dams usually break down rapidly soon after the formation of the lake. Regarding hazard mitigation, prompt evaluation of the stability of the landslide dam is crucial. Based on a Japanese dataset, this study utilized the logistic regression method and the jack-knife technique to identify the important geomorphic variables, including peak flow (or catchment area), dam height, width and length in sequence, affecting the stability of landslide dams. The resulting high overall prediction power demonstrates the robustness of the proposed logistic regression models. Accordingly, the failure probability of a landslide dam can also be evaluated based on this approach. Ten landslide dams (formed after the 1999 Chi-Chi Earthquake, the 2008 Wenchuan Earthquake and 2009 Typhoon Morakot) with complete dam geometry records were adopted as examples of evaluating the failure probability. The stable Tsao-Ling landslide dam, which was induced by the Chi-Chi earthquake, has a failure probability of 27.68% using a model incorporating the catchment area and dam geometry. On the contrary, the Tangjiashan landslide dam, which was artificially breached soon after its formation during the Wenchuan earthquake, has a failure probability as high as 99.54%. Typhoon Morakot induced the Siaolin landslide dam, which was breached within one hour after its formation and has a failure probability of 71.09%. Notably, the failure probability of the earthquake induced cases is reduced if the catchment area in the prediction model is replaced by the peak flow of the dammed stream for these cases. In contrast, the predicted failure probability of the heavy rainfall-induced case increases if the high flow rate of the dammed stream is incorporated into the prediction model. Consequently, it is suggested that the prediction model using the peak flow as causative factor should be used to evaluate the stability of a landslide dam if the peak flow is available. Together with an estimation of the impact of an outburst flood from a landslide-dammed lake, the failure probability of the landslide dam predicted by the proposed logistic regression model could be useful for evaluating the related risk. (C) 2010 Elsevier B.V. All rights reserved.Item type:Item, Crystal Quality and Light Output Power of GaN-Based LEDs Grown on Nanoporous Patterned Sapphire Substrate(2014) ;Chen, Chien-Chih ;Yap, Chun-Yan ;Hsu, Wen-Yang ;Kuo, Cheng-TaTsai, Tzong-LiangThe crystal quality and light output power of GaN-based LEDs grown on nanoporous patterned sapphire substrate (NPSS) were investigated. NPSS was prepared using an anodized aluminum oxide (AAO) layer. It was found that the crystal quality of GaN-based LEDs grown on NPSS was better than that on micron-sized patterned sapphire substrate (MPSS) and conventional sapphire substrate. However, the light output power of GaN-based LEDs grown on NPSS was smaller than that on MPSS because the light extraction efficiency (LEE) of MPSS was much larger than that of NPSS. (C) 2014 The Electrochemical Society. All rights reserved.Item type:Item, Particle image velocimetry measurement of jet impingement in a cylindrical chamber with a heated rotating disk(2013-10-01) ;Liu, Yao-Hsien ;Tseng, Li-Wei ;Huang, Chih-Yung ;Lin, Kung-LiangChen, Chien-ChihWe studied the flow field of a jet impingement on a rotating heated disk to simulate the flow field surrounding the rotating disk of a chemical vapor deposition (CVD) reactor, which is widely used for large-scale production of thin-films and semiconductor materials. The flow field influences the growth rate and deposition uniformity, and is subject to the combined effects of buoyancy, centrifugal, and flow inertia forces that occur during the deposition process. The study investigated various flow-cell sizes and locations, such as the inlet flow-rate (1-10 slpm), jet-to-disk temperature difference (40-80 degrees C), and disk rotational speeds (0-500 rpm). Particle image velocimetry (PIV) was used to measure the flow-velocity field and flow-streamlines in the test chamber. The time-averaged axial and radial velocity profiles near the disk were used to determine the variations in flow velocity resulting from rotation and heating. Upward buoyancy forces, caused by the heated disk, produce flow cells and break the flow uniformity above the disk. When the rotational Reynolds number increases, the rotational effect eventually dominates the flow field that increases the flow velocity and generates flow cells near the chamber wall. Flow regime maps of these flow patterns were constructed, based on the Grashof number and rotational Reynolds number. (c) 2013 Elsevier Ltd. All rights reserved.Item type:Item, Evolution of Bottom c-Plane on Wet-Etched Patterned Sapphire Substrate(2013) ;Chen, Chien-Chih ;Hsiao, Feng Ching ;Lin, Bo-Wen ;Hsu, Wen-ChingWu, YewChung SermonWet-etched pattern sapphire substrate (PSS) has been employed to improve the epitaxy of GaN-based LEDs. It was found that the crystal quality and performance of LEDs improved with decrease in c-plane areas of PSS. However, further decrease in bottom c-plane areas makes epitaxy of GaN film very difficult. In this research, the evolution of bottom c-plane was investigated through a systematic study. It was found that epitaxy difficulty might be due to the appearance of 6C facets {4 (1) over bar(3) over bar 18} and the disappearance of bottom c-plane. (C) 2013 The Electrochemical Society.Item type:Item, Using Fluorine-ion Implanted a-Si Layer to Reduce Ni Contamination and Passivate the Defects in NILC poly-Si(2010) ;Chen, Chien-Chih ;Wu, YewChung Sermon ;材料科學與工程學系Department of Materials Science and EngineeringThe grain boundaries which included dangling bonds in Ni-metal-induced lateral crystallization (NILC) poly-Si TFT would trap Ni and NiSi2 precipitates. This phenomenon resulted in threshold voltage shifting and lower field-effect mobility. To resolve this issue, the a-Si layer with fluorine-ion implanted was used as gettering layer to reduce Ni contamination and passivate the dangling bonds in the active layer. It was found that the F-G layer could not only reduce the Ni contamination but also passivate the defects in NILC poly-Si.Item type:Item, Enhanced performance and reliability of NILC-TFTs using FSG buffer layer(2012-02-15) ;Chen, Chien-Chih ;Wu, YewChung Sermon ;Chang, Chih-Pang ;材料科學與工程學系Department of Materials Science and EngineeringA new manufacturing method for Ni-metal-induced lateral crystallization thin film transistors (NILC-TFTs) using fluorine-silicate-glass (FSG) was proposed. In FSG-TFTs, fluorine ion was implanted into the buffer oxide layer to form FSG before NILC processes. It was found FSG-TFTs exhibit high field-effect mobility, low threshold voltage, low subthreshold slope, high ON/OFF current ratio, low trap state density, low interface trap state density, and good reliability compared with typical NILC-TFTs. (c) 2011 Elsevier B.V. All rights reserved.Item type:Item, NUDA: A Non-Uniform Debugging Architecture and Nonintrusive Race Detection for Many-Core Systems(2012-02-01) ;Wen, Chi-Neng ;Chou, Shu-Hsuan ;Chen, Chien-Chih ;Chen, Tien-Fu資訊工程學系Traditional debugging methodologies are limited in their ability to provide debugging support for many-core parallel programming. Synchronization problems or bugs due to race conditions are particularly difficult to detect with existing debugging tools. Most traditional debugging approaches rely on globally synchronized signals, but these pose their own problems in terms of scalability. The first contribution of this paper is to propose a novel non-uniform debugging architecture (NUDA) based on a ring interconnection schema. Our approach makes hardware-assisted debugging both feasible and scalable for many-core processing scenarios. The key idea is to distribute the debugging support structures across a set of hierarchical clusters while avoiding address overlap. The design strategy allows the address space to be monitored using non-uniform protocols. Our second contribution is to propose a nonintrusive approach to lockset-based race detection supported by the NUDA. A non-uniform page-based monitoring cache in each NUDA node is used to keep track of the access footprints. The union of all the caches can serve as a race detection probe without disturbing execution ordering. Using the proposed approach, we show that parallel race bugs can be precisely captured, and that most false-positive alerts can be efficiently eliminated at an average slowdown cost of only 1.4-3.6 percent. The net hardware cost is relatively low, so that the NUDA can easily be scaled to increasingly complex many-core systems.