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Author: search.filters.author.Chen, Chih-LungSubject: search.filters.subject.LDPC

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    A 7.72 Gb/s LDPC-CC Decoder with Overlapped Architecture for Pre-5G Wireless Communications
    (2016-01-01)
    Lin, Chia-Lung
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    Liu, Rong-Jie
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    Chen, Chih-Lung
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    Chang, Hsie-Chia
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    Lee, Chen-Yi
    LDPC block codes (LDPC-BCs) have attracted great interests in recent years by highly parallel computation and good bit-error-rate performance, and one of the decoder implementation issues is high routing complexity. LDPC convolutional codes (LDPC-CCs) not only release routing complexity but also are natural to dynamic length of data frame. Thus, the codes are very suitable for video stream and pre-5G wireless communication systems. LDPC-CC decoder is composed of several concatenated processors, where the long FIFOs are usually the bottleneck of area and decoding latency. To improve hardware efficiency, we use overlapped architecture to share partial FIFO between processors. Furthermore, check node unit and hybrid-partitioned FIFO are proposed to increase throughput and pipeline efficiency. The measurement results of test chip in 65nm technology show that our work can achieves 7.72 Gb/s under 322MHz operating frequency. The decoder with 6 processors occupies an area of 1.19 mm(2), drawing 410.5 mW of power with an energy efficiency of 8.75pJ/bit/proc.
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    A 11.5-Gbps LDPC Decoder Based on CP-PEG Code Construction
    (2009)
    Chen, Chih-Lung
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    Lin, Kao-Shou
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    Chang, Hsie-Chia
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    Fang, Wai-Chi
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    Lee, Chen-Yi
    In this paper, a LDPC decoder chip based on CPPEG code construction is presented. The (2048, 1920) irregular LDPC code generated by CP-PEG algorithm has better performance than other PEG-based codes; however, the large check node degrees introduced by high code-rate 15/16 become the implementation bottleneck. To design such a high coderate LDPC decoder, our approach features variable-node-centric sequential scheduling to reduce iteration number, single piplelined decoder architecture to lessen the message storage memory size, as well as optimized check node unit to further compress the register number. Overall 73% message storage memory is saved as compared with traditional architecture. Fabricated in 90nm 1P9M CMOS technology, a test deocder chip could achieve maximum 11.5 Gbps throughput under 1.4V supply voltage with core area of 2.7 x 1.4 mm(2). The energy efficiency is only 0.033 nJ/bit with 5.77 Gbps at 0.8V to meet IEEE 802.15.3c requirements.