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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Chen, Hung-MingSubject: search.filters.subject.Algorithms

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Now showing 1 - 4 of 4
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    Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation
    (2014-11-01)
    Wang, Chun-Kai
    ;
    Chang, Yeh-Chi
    ;
    Chen, Hung-Ming
    ;
    Chin, Ching-Yu
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    電子工程學系及電子研究所
    This work tackles a problem of clock power minimization within a skew constraint under supply voltage variation. This problem is defined in the ISPD 2010 benchmark. Unlike mesh and cross link that reduce clock skew uncertainty by multiple driving paths, our focus is on controlling skew uncertainty in the structure of the tree. We observe that slow slew amplifies supply voltage variation, which induces larger path delay variation and skew uncertainty. To obtain the optimality, we formulate a symmetric clock tree synthesis as a mathematical programming problem in which the slew effect is considered by an NLDM-like cell delay variation model. A symmetry-to-asymmetry tree transformation is proposed to further reduce wire loading. Experimental results show that the proposed four methods save up to 20% of clock tree capacitance loading. Beyond controlling slew to suppress supply-voltage-variation-induced skew, we also discuss the strategies of clock tree synthesis under variant variation scenarios and the limitations of the ISPD 2010 benchmark.
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    Agglomerative-Based Flip-Flop Merging and Relocation for Signal Wirelength and Clock Tree Optimization
    (2013-07-01)
    Liu, Sean Shih-Ying
    ;
    Lo, Wan-Ting
    ;
    Lee, Chieh-Jui
    ;
    Chen, Hung-Ming
    ;
    電子工程學系及電子研究所
    In this article, we propose a flip-flop merging algorithm based on agglomerative clustering. Compared to previous state-of-the-art on flip-flop merging, our proposed algorithm outperforms that of Chang et al. [2010] and Wang et al. [2011] in all aspects, including number of flip-flop reductions, increase in signal wirelength, displacement of flip-flops, and execution time. Our proposed algorithm also has minimal disruption to original placement. In comparison with Jiang et al. [2011], Wang et al. [2011], and Chang et al. [2010], our proposed algorithm has the least displacement when relocating merged flip-flops. While previous works on flip-flop merging focus on the number of flip-flop reduction, we further evaluate the power consumption of clock tree after flip-flop merging. To further minimize clock tree wirelength, we propose a framework that determines a preferable location for relocated merged flip-flops for clock tree synthesis (CTS). Experimental results show that our CTS-driven flip-flop merging can reduce clock tree wirelength by an average of 7.82% with minimum clock network power consumption compared to all of the previous works.
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    A Study of Row-Based Area-Array I/O Design Planning in Concurrent Chip-Package Design Flow
    (2013-03-01)
    Lee, Ren-Jie
    ;
    Chen, Hung-Ming
    ;
    交大名義發表
    ;
    National Chiao Tung University
    IC-centric design flow has been a common paradigm when designing and optimizing a system. Package and board/system designs are usually followed by almost-ready chip designs, which causes long turn-around time communicating with package and system houses. In this article, the realizations of area-array I/O design methodologies are studied. Different from IC-centric flow, we propose a chip-package concurrent design flow to speed up the design time. Along with the flow, we design the I/O-bump (and P/G-bump) tile that combines I/O (and P/G) and bump into a hard macro with the considerations of I/O power connection and electrostatic discharge (ESD) protection. We then employ an I/O-row based scheme to place I/O-bump tiles with existed metal layers. By such a scheme, it reduces efforts in I/O placement legalization and the redistribution layer (RDL) routing. With the emphasis on package design awareness, the proposed methods map package balls onto chip I/Os, thus providing an opportunity to design chip and package in parallel. Due to this early study of I/O and bump planning, faster convergence can be expected with concurrent design flow. The results are encouraging and the merits of this flow are reassuring.
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    Performance-Constrained Voltage Assignment in Multiple Supply Voltage SoC Floorplanning
    (2009-12-01)
    Wu, Meng-Chen
    ;
    Lu, Ming-Ching
    ;
    Chen, Hung-Ming
    ;
    Jou, Jing-Yang
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    電子工程學系及電子研究所
    Using voltage island methodology to reduce power consumption for System-on-a-Chip (SoC) designs has become more and more popular recently. Currently this approach has been considered either in system-level architecture or postplacement stage. Since hierarchical design and reusable intellectual property (IP) are widely used, it is necessary to optimize floorplanning/placement methodology considering voltage islands generation to solve power and critical path delay problems. In this article, we propose a floorplanning methodology considering voltage islands generation and performance constraints. Our method is flexible and can be extended to hierarchical design. The experimental results on some MCNC benchmarks show that our method is effective in meeting performance constraints and can simultaneously consider the tradeoff between power routing cost and total power dissipation.