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Investigation of Data Pattern Effects on Nitride Charge Lateral Migration in a Charge Trap Flash Memory by Using a Random Telegraph Signal Method
(2018-01-01)
Liu, Y. H.
;
Lin, H. Y.
;
Jiang, C. M.
;
Wang, Tahui
;
Tsai, W. J.
Data pattern effects on nitride charge lateral migration and V-t retention loss in a charge trap flash memory is investigated. We use channel hot electron program and band-to-band tunneling hot hole erase to inject different amounts of electrons and holes at the two sides of a channel in a SONOS cell. An interface oxide trap near an injected charge packet and its associated random telegraph signal (RTS) are used as an internal probe to detect a local channel potential change resulting from trapped charge lateral migration. Vt retention loss and RTS in various charge storage patterns are characterized and analyzed. At a similar built-in electric field, nitride trapped holes are found to be more mobile than trapped electrons in lateral migration.
Chip-Level Characterization and RTN-Induced Error Mitigation beyond 20nm Floating Gate Flash Memory
(2018-01-01)
Lin, T. W.
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Ku, S. H.
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Cheng, C. H.
;
Lee, C. W.
;
Ijen-Huang
Vt instability caused by random telegraph noise (RTN) in floating gate flash memories beyond 20nm is studied comprehensively. Experiments reveal that the RTN would cause Vt distribution with a kinked tail which re-distributes to a "Gaussian-like" shape rapidly and was measured by the self established Budget Product Tester (BPT). A Multi-Times Verify (MTV) algorithm to mitigate the statistical tail, thus enlarging operation window is also exhibited by BPT. In further, a probability model to portray the compact Vt distribution under MTV is proposed. Finally, the impact of MTV on lowering the requirement of Error-correcting code (ECC) bit is also demonstrated.
Error Characterization and ECC Usage Relaxation beyond 20nm Floating Gate NAND Flash Memory
(2018-01-01)
Ku, S. H.
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Lin, T. W.
;
Cheng, C. H.
;
Lee, C. W.
;
Chen, Ti-Wen
Endurance of floating gate flash memories at 19nm node and beyond is studied comprehensively. Experiments reveal that the random telegraph noise (RTN) would degrade the read margin with a tail, which quickly reshapes into a symmetric Gaussian form in a lightly-stressed state. After heavy stress, the lower part of tail would spread further while the upper part keeps roughly overlapped with that during fresh. This unique behavior, which was firstly measured by the self-established Budget Product Tester (BPT), can be explained by stress-induced hole trap creation. To investigate the impact of RTN on operation window, a novel algorithm of Multi-Times-Verify accompanied with the optimal Read-Retry (MTVR2) is proposed and validated by BPT. The advantage of MTVR2 to reduce the requirement of Error-Correcting Code (ECC) bit is demonstrated. Finally, the improvement of bit error rate (BER) in TLC operation with MTVR(2 )is also evaluated.
Analysis and Realization of TLC or even QLC Operation with a High Performance Multi-times Verify Scheme in 3D NAND Flash memory
(2018-01-01)
Lu, C. C.
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Cheng, C. C.
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Chiu, H. P.
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Lin, W. L.
;
Chen, T. W.
Feasibility of multi-times verify (MTV) scheme on triple-level cell (TLC) and quad-level cell (QLC) operations of charge-trap storage 3D NAND memories is investigated comprehensively. Results reveal that random telegraph noise (RTN) and program noise are the major factors affecting lower (LB) and upper boundaries (HB) of Vt distribution, respectively. Enlargement of operation window and reduction of ECC usage with MTV scheme to mitigate RTN-induced LB tail are demonstrated on TLC and QLC operations. In addition, the impact of program noise on HB Vt under various process conditions and ISPP steps is studied experimentally and also explained by our Monte Carlo simulator. Finally, program performance and reserved margin with and without MTV scheme applied on TLC and QLC operation are demonstrated.
Variations of V-t Retention Loss in a SONOS Flash Memory Due to a Current-Path Percolation Effect
(2011-04-01)
Chou, Y. L.
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Chung, Y. T.
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Wang, Tahui
;
Ku, S. H.
;
Zou, N. K.
Discrete nitride program charge loss in a small-area SONOS Flash memory cell during retention is observed. Our measurement shows that a retention V-t of a programmed SONOS cell exhibits a stepwise evolution with retention time. Individual single-program charge-loss-induced threshold voltage shifts (Delta V-t) are characterized. We find the following: 1) The magnitude of Delta V-t exhibits an exponential distribution, which is believed due to a current-path percolation effect caused by random program charges and substrate dopants, and 2) program-state V-t retention loss has large variations in different cells and P/E cycles due to the percolation effect. We develop a Monte Carlo analysis to take into account the distribution of Delta V-t and a tunneling front model to study the spread of a retention V-t distribution in a SONOS Flash memory.
Polycrystalline-Silicon Channel Trap Induced Transient Read Instability in a 3D NAND Flash Cell String
(2016-01-01)
Tsai, Wen-Jer
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Lin, W. L.
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Cheng, C. C.
;
Ku, S. H.
;
Chou, Y. L.
Vt instability caused by grain-boundary trap (GBT) in the poly-crystalline silicon (poly-Si) channel of a 3D NAND string are comprehensively studied. Experimental results reveal that trapping/detrapping of GBT would cause transient cell current with a time constant of lOus or longer, and this transient is strongly affected by the bias history. Sensing offset between program/erase verify (PV/EV) and read (RD) results in "pseudo" charge loss/gain that reduces the sensing margin. Modified EV, PV, or RD bias schemes are suggested to mitigate this effect.
Poly-Silicon Trap Position and Pass Voltage Effects on RTN Amplitude in a Vertical NAND Flash Cell String
(2016-08)
Chou, Y. L.
;
Wang, Tahui
;
Lin, Mercator
;
Chang, Y. W.
;
Liu, Lenvis
We investigate the dependence of random telegraph noise (RTN) on a poly-silicon trap position in a 3D vertical channel and charge-trapping NAND flash cell string. We characterize RTN in read current of each cell of a string at different read and pass voltages. RTN characteristics resulting from a trap in a read cell or in a pass cell are differentiated. A method to identify a poly-silicon trap position in a NAND string is proposed. We perform the 3D TCAD simulation to calculate channel electron density in a string. Measured RTN characteristics can be explained by current-path percolation and channel carrier screening effects. The distribution of RTN amplitudes in NAND strings is characterized.
Cell Endurance Prediction from a Large-area SONOS Capacitor
(2009)
Lee, C. H.
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Tu, W. H.
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Gu, S. H.
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Wu, C. W.
;
Lin, S. W.
Endurance considerations induced by the degadation of top and bottom oxides are proposed for a SONOS memory. First, a correlation is found between the widespread C-V curves induced by interface generation and cycling numbers (cyc. #). Unlike V-FB (accumulation region), V-T (inversion region) shows a much severe shift. Inter-face state (N-it) is identified as a key factor even when a 2nm bottom oxide is used. Moreover, charge to breakdown (Q(BD)) for an ONO capacitor under positive and negative constant current stress (CCS) is investigated. Our study reveals that QBD of such stacks strongly depends on the top oxide thickness. A field enhancement induced by charges in a trapping nitride layer is the root cause. Based on Weibull statistics, the risk of dielectric breakdown for both blocking layers is then evaluated.
In-situ TEM Study of Electromigration in Cu lines
(2009)
Liao, C. N.
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Chen, K. C.
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Wu, W. W.
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Chen, L. J.
;
Tu, K. N.
The density of electric current passing through interconnecting wires in integrated circuits (IC) is increasing with continuous miniaturization of IC. Under a high operating temperature and large electric current density, some voids and hillocks may form in the interconnecting wires due to electromigration (EM), leading to device failures eventually. In this study atomic-scale EM in unpassivated copper lines has been investigated in ultrahigh vacuum by in situ transmission electron microscopy (TEM). The EM-induced atomic surface diffusion was found to be crystal-orientation dependent and occurred preferentially on the {111} planes along < 110 > directions. The high-resolution TEM images and the electron diffraction patterns of a (111)-oriented Cu grain in the Cu line revealed an EM-induced step structure at surface. Moreover, the triple point where a twin boundary meets a grain boundary was found to slow down atomic EM at grain boundaries because of the incubation time of nucleation of a new step at the triple point. The long incubation time slows down the overall rate of atomic transport. The results suggest that the EM reliability of Cu interconnects may be enhanced by forming a high density of nanometer scaled twins in the coarse-grain Cu wires.
Overall Operation Considerations for a SONOS-based Memory
(2009)
Lee, C. H.
;
Tu, W. H.
;
Chong, L. H.
;
Gu, S. H.
;
Chen, K. F.
Erase characteristics of a SONOS-based structure are emulated not only for n(+)-poly and p(+)-poly gates but also for TaN-gate+Al2O3 combination. By incorporating our previous studies, performances including program, erase, and read disturb can be reviewed for both SONOS and TANOS devices. Unsurprisingly, it is hard to satisfy all requirements by using a SONOS device. In a TANOS device, an optimal bottom oxide thickness can be specified with the consideration of the three factors simultaneously. Moreover, it is found that conventional extrapolation methodology is inadequate to predict the lifetime of a TANOS device and tends to under-estimate the tolerable read bias.

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