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A 64-CHANNEL WIRELESS NEURAL SENSING MICROSYSTEM WITH TSV-EMBEDDED MICRO-PROBE ARRAY FOR NEURAL SIGNAL ACQUISITION
(2017-01-01)
Huang, Yu-Chieh
;
Huang, Po-Tsang
;
Hu, Yu-Chen
;
Wu, Shang-Lin
;
You, Yan-Huei
To enhance the signal integrity of high-density neural-sensing signals, this work presents an implantable high spatial resolution mu-probe array with through-silicon via (TSV) 2.5D integration technology that realizes a miniaturized implantable device on flexible printed circuit (FPC) interposer. The proposed microsystem was composed of two 32-channel neural sensing chips and one radio frequency chip for neural signal processing. The mu-probe array can achieve better signal-to-noise ratio with neural-signal acquisition and processing circuit composed of a pseudo-resistor-based analog front-end amplifier. Moreover, a receiving antenna is also implemented on the backside of FPC for wireless data and power transmission. The feasibility of the proposed mu-probe array, Tx and Rx antenna, 32-channel neural sensing circuits in the 64-channel wireless microsystem have been successfully demonstrated for future integration and animal experiments.
Development of Bumpless Stacking With Bottom-Up TSV Fabrication
(2017-04-01)
Lee, Shih-Wei
;
Chen, Kuan-Neng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 3-D integration technology using bump less stacking based on a new bottom up Cu electroplating method without backside Cu chemical-mechanical planarization removal is presented in this paper. The approach successfully achieves via plating without thick Cu overburden by probing unique bottom electrodes for different I/O ports of TSV without additional steps in the conventional processes. The concepts and fabrication processes are described in detail. The results obtained from through silicon via (TSV) daisy chains show excellent electrical characteristics and good reliability in leakage current measurement. The proposed approach therefore has potential for low-cost via-last 3-D integration.
Modeling and Characterization of TSV Capacitor and Stable Low-Capacitance Implementation for Wide-I/O Application
(2015-06-01)
Chang, Yao-Yen
;
Ko, Cheng-Ta
;
Yu, Tsung-Han
;
Hsieh, Yu-Sheng
;
Chen, Kuan-Neng
Equations of the electric field, surface charge, and silicon capacitance with respect to the surface potential of single through-silicon via (TSV) are derived by Poisson\'s equation. Four kinds of charges such as the electrons, holes, and ionized donor/acceptor charges in the p-type silicon substrate are brought into the equations. The numerical results of the surface charge show identical plots to planar MOS capacitor when the TSV radius is larger than 1 mu m. After presenting the fundamental C-V characteristics of one TSV capacitor, a simple design for gaining a stable low TSV capacitance value within a wide operating window (vertical bar V-ow vertical bar = 20 V) is proposed. Cu TSVs in this design are then demonstrated in the scheme of the wafer-level Cu/Sn to BCB hybrid bonding. The design gives the rational power consumption and delay, and the guideline for physical IC design is described in this paper. Without the oxide-trapped charge Q(ot) engineering in TSV oxide liner, neither considerations of the V-FB shifts nor the doping-type selection in silicon substrate, the design facilitates IC engineers to plan the high-speed TSVs at a specific location and to save the cost from TSV engineering simultaneously.
Device Characteristics of TSV-Based Piezoelectric Resonator With Load Capacitance and Static Capacitance Modification
(2015-03-01)
Shih, Jian-Yu
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Chen, Yen-Chi
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Chiu, Chih-Hung
;
Lo, Chung-Lun
;
Chang, Chi-Chung
The piezoelectric resonator device based on 3-D integration technologies and hermetic sealing bonding is presented with conventional semiconductor process. To pursue small form factor, high-performance, and cost-effective technologies, this through-silicon via (TSV)-based resonator is fabricated by CuSn eutectic bonding for hermeticity, wafer-level thinning, and Cu TSVs interconnection, while high-temperature cofired ceramic (HTCC) with metal lid is applied in the conventional resonator devices. The device characteristics and reliability of TSV-based resonator reveal it has great performance and outstanding quality. In addition, the device characteristics with load capacitance and its improvement through modification of the isolation in TSV-based substrate are discussed in this research. Demonstrations of these characteristics show that the TSV-based resonator possesses advantages and compatibility with current semiconductor process, as well as the manufacturability compared with the conventional metal lid with HTCC enclosures.
Sealing Bump With Bottom-Up Cu TSV Plating Fabrication in 3-D Integration Scheme
(2013-05-01)
Chiang, Cheng-Hao
;
Kuo, Li-Min
;
Hu, Yu-Chen
;
Huang, Wen-Chun
;
Ko, Cheng-Ta
A sealing bump approach for the simplification of the conventional bottom-up copper through-silicon via (TSV) plating process flow is developed to reduce the process steps and increase the throughput without sacrificing the structure integrity and electrical performance. In this approach, TSV and bump formation can be achieved simultaneously through the bottom-up plating. Results from the analysis reveal excellent electrical characteristics and quality examination, which indicate that the proposed approach may be a good candidate for the TSV fabrication in 3-D integration.
Backside-Process-Induced Junction Leakage and Process Improvement of Cu TSV Based on Cu/Sn and BCB Hybrid Bonding
(2013-03-01)
Chang, Yao-Jen
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Ko, Cheng-Ta
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Yu, Tsung-Han
;
Chiang, Cheng-Hao
;
Chen, Kuan-Neng
Wafer-level 3-D integration using Cu through-silicon vias (TSVs) and fine-pitch Cu/Sn-BCB hybrid bonding is investigated with electrical leakage current. With the well-fabricated Cu TSVs and Cu/Sn bond structures, the leakage current path in this scheme due to backside process was found, and the corresponding mechanism is discussed. The leakage current can be solved by the modified backside process. The improved 3-D integration scheme shows extremely low leakage current and no visible defects inside Cu TSV.
Electrical and Reliability Investigation of Cu TSVs With Low-Temperature Cu/Sn and BCB Hybrid Bond Scheme
(2013-01-01)
Chang, Yao-Jen
;
Ko, Cheng-Ta
;
Chen, Kuan-Neng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A wafer-level 3-D integration scheme using Cu through-silicon vias (TSVs) and fine-pitch Cu/Sn-BCB hybrid bonding was developed and investigated with electrical characterization and reliability assessment. The hybrid bonding could be achieved below 250 degrees C. Low Kelvin resistance and stable daisy chain resistance were achieved in 5- and 10-mu m TSV test structures across the whole wafer. Without obvious deterioration in reliability test results, the integrated Cu TSV and hybrid bond scheme can be potentially designed for 3-D integration applications.

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