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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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Author: search.filters.author.Chen, MJSubject: search.filters.subject.MOSFETs

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Now showing 1 - 5 of 5
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    Edge hole direct Tunneling leakage in ultrathin gate oxide p-channel MOSFETs
    (2001-12-01)
    Yang, KN
    ;
    Huang, HT
    ;
    Chen, MJ
    ;
    Lin, YM
    ;
    Yu, MC
    This paper examines the edge direct tunneling (EDT) of holes from p(+) polysilicon to underlying p-type drain extensions in off-state p-channel MOSFETs having ultrathin gate oxides that are 1.2 nm-2.2 nm thick. It is for the first time found that for thinner oxides, hole EDT is more pronounced than both conventional gate-induced drain leakage (GIDL) and gate-to-channel tunneling. As a result, the induced gate and drain leakage is more accurately measured per unit gate width. Terminal currents versus input voltage are measured from a CMOS inverter with gate oxide thickness T-OX = 1.23 nm, exhibiting the impact of EDT in two standby modes. For the first time, a physical model is derived for the oxide field E-OX at the gate edge by accounting for the heavy and light holes' subbands in the quantized accumulation polysilicon surface. This model relates E-OX to the gate-to-drain voltage, oxide thickness, and doping concentration of the drain extension. Once E-OX is known, an existing direct tunneling (DT) model consistently reproduces EDT current-voltage (I-V), and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to hole EDT is projected.
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    A new process-variation-immunity method for extracting capacitance coupling coefficients in flash memory cells
    (2002-07-01)
    Cho, CYS
    ;
    Chen, MJ
    ;
    Lin, JH
    ;
    Chen, CF
    ;
    電子工程學系及電子研究所
    Overestimation of capacitance coupling coefficients in flash memory cells is encountered in the subthreshold slope method. By means of a two-parameters subthreshold current model I-D = I-o exp[q(V-GB - nV(SB))/nkT], a mathematical formulation of the subthreshold swing ratio in the subthreshold slope method is constructed to isolate the measurement errors caused by process variations from the errors traditionally caused by bulk capacitance coupling. To minimize the effect of process variations, a new method is developed based on the model. In this method, the control gate voltage shift due to weak body effect is measured in flash memory cells in subthreshold, while the corresponding slope factor n is adequately deduced from threshold voltage versus source-to-substrate bias measurement in dummy devices. The corrected capacitance coupling coefficients show large improvements compared to the design values, and the updated errors are found to be close to that caused solely by bulk capacitance coupling. The method is also fast since only a small source-to-substrate bias of 0.1 V is needed for implementation of weak body effect, and thereby it can be used as an in-line monitor of capacitance coupling coefficients.
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    Improved subthreshold slope method for precise extraction of gate capacitive coupling coefficients in stacked gate and source-side injection flash memory cells
    (2004-07-01)
    Cho, CYS
    ;
    Chen, MJ
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    Existing subthreshold slope methods are shown to be far from accurate in extracting gate capacitive coupling coefficient alpha(G) in stacked gate flash memory cells. The origin of the error is systematically identified: (i) process variations induced mismatch and (ii) underlying bulk capacitive coupling. To alleviate such drawbacks, a new version of the subthreshold slope method at room temperature is established: alpha(G) = 0.06(n(f) - alpha(B))/s(f), where the subthreshold swing s(f) is from flash memory cells, the subthreshold slope factor nf is from dummy transistors via threshold voltage against source-to-substrate bias measurement, and the bulk coupling coefficient alpha(B) is from a linear extension of the dimensional dependencies in the literature. The resulting alpha(G) of around 0.55 again agrees consistently with those dependencies and once drain and source coupling experiment is performed, the relation of Sigma alpha(i) approximate to 1 is achieved for all involved coupling coefficients alpha(i)'s.. The sidewall source-side injection flash memory cells are also investigated. With the improved method, this manufacturing process is proved free of process variations issue and is characterized with alpha(G) of 0.374 and fringing capacitance of 0.204 fF. (C) 2004 Elsevier Ltd. All rights reserved.
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    Separation of channel backscattering coefficients in nanoscale MOSFETs
    (2004-09-01)
    Chen, MJ
    ;
    Huang, HT
    ;
    Chou, YC
    ;
    Chen, RT
    ;
    Tseng, YT
    Channel backscattering coefficients in the kBT layer (near the source) of 1.65-nm-thick gate oxide, 68-nm gate length bulk n-channel MOSFETs are systematically separated into two distinct components: the quasithermal-equilibrium mean-free-path for backscattering and the width of the kBT layer. Evidence to confirm the validity of the separation procedure is further produced: 1) the near-source channel conduction-band profile; 2) the existing value of kBT layer width from the sophisticated device simulation; and 3) an analytic temperature-dependent drain current model for the channel backscattering coefficients. The findings are also consistent with each other and therefore corroborate channel backscattering as the origin of the coefficients. Other interpretations and clarifications are determined with respect to the very recently released Monte Carlo particle simulation. Consequently, it can be reasonably claimed that the separated components, as well as their dependencies on temperature and bias, are adequate while being used to describe the operation of the devices undertaken within the framework of the channel backscattering theory.
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    A novel self-aligned highly reliable sidewall split-gate flash memory
    (2006-03-01)
    Cho, CYS
    ;
    Chen, MJ
    ;
    Chen, CF
    ;
    Tuntasood, P
    ;
    Fan, DT
    A self-aligned sidewall split-gate Flash memory cell is fabricated with overerase immunity. Particularly, the sidewall corner of the floating-gate is deliberately rounded to release the electric field lines encountered in the poly-to-poly erase. The unit cell size of 12.7 F-2 (F is the feature size), formed in a 32-Mb NOR architecture, and the acceptable erase speed of 20 ms for block erase (512 K bits, 16 pages) are quite competitive. Endurance cycles up to 105 confirm the novel cell to be highly reliable as compared with the conventional source-side erase scheme. The bake experiment at 250 degrees C before and after program/erase cycles indicates the cell not only free of extrinsic defects in the manufacturing process but also experiencing excellent retention characteristics. Disturb effects during the programming and read-out operations are examined in detail and the operating conditions for disturbs inhibition are readily determined. We eventually elaborate on the differences between the proposed cell structure and existing ones, as well as on the NAND architecture application.