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Author: search.filters.author.Chen, Ming-JerSubject: search.filters.subject.MOSFET

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Now showing 1 - 10 of 13
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    An Extreme Surface Proximity Push for Embedded SiGe in pMOSFETs Featuring Self-Aligned Silicon Reflow
    (2010-09-01)
    Lin, Da-Wen
    ;
    Chen, Chien-Liang
    ;
    Chen, Ming-Jer
    ;
    Wu, Chung-Cheng
    ;
    電子工程學系及電子研究所
    This letter proposes a novel process to modulate the distance, or proximity, between the tip of embedded silicon-germanium (e-SiGe) and the channel region in pMOSFETs. Traditionally, sophisticated etching treatment is adopted in a spacer structure; however, process-induced variation in the e-SiGe proximity may lead to serious variation in pMOSFET performance. In this letter, an extremely close proximity is achieved using self-aligned silicon reflow (SASR) in hydrogen ambient. As opposed to conventional approaches which have e-SiGe proximity determined by spacer width, the tip of e-SiGe with SASR can be positioned flush with the gate edge, as corroborated by both the TEM analyses and TCAD simulation. A significant improvement in pMOSFET performance is also measured.
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    Gate Direct Tunneling Current in Uniaxially Compressive Strained nMOSFETs: A Sensitive Measure of Electron Piezo Effective Mass
    (2011-01-01)
    Lee, Wei-Han
    ;
    Chen, Ming-Jer
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    Currently, both the band-structure calculation and the mobility measurement are used to assess the electron piezo-effective-mass coefficients in strained nMOSFETs. In this paper, we present a new experimental method through a fitting of the strain-altered electron gate direct tunneling current. The core of this method lies in the sensitivity of the direct tunneling to the position of the subband level in the presence of the electron piezo-effective-mass coefficients. First, a correction-coefficient generating expression is systematically constructed to compensate for the error in the subband levels due to the use of a triangular potential approximation. Then, with the known deformation potential constants and uniaxially compressive stress in the channel as inputs, a strain quantum simulator is carried out. The resulting gate direct tunneling current is used to fit experimental data, thus leading to the values of the piezo-effective-mass coefficients associated with the twofold and fourfold valleys. The comparison of the extracted piezo-effective-mass coefficients to those published in the literature is made.
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    Reproducing subthreshold characteristics of metal-oxide-semiconductor field effect transistors under shallow trench isolation mechanical stress using a stress-dependent diffusion model
    (2006-08-01)
    Sheu, Yi-Ming
    ;
    Yang, Sheng-Jier
    ;
    Wang, Chih-Chiang
    ;
    Chang, Chih-Sheng
    ;
    Chen, Ming-Jer
    N-channel metal-oxide-semiconductor field effect transistors (MOSFETs) with a lightly doped well exhibit subthreshold current versus voltage (I-V) characteristics that are sensitive to shallow trench isolation (STI) mechanical stress. Such striking dependencies offer the opportunity to validate a proposed two-dimensional (2D) process model that relates the impurity diffusion to the mechanical stress throughout the substrate. With the assistance of sophisticated process/device simulations, the model appears to satisfactorily reproduce subthreshold I-V characteristics for different active area lengths and different substrate biases. The stress-dependent point defect equilibrium concentration and diffusion model are also implemented to evaluate the stress effect on transient enhanced diffusion.
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    Temperature-oriented experiment and simulation as corroborating evidence of MOSFET backscattering theory
    (2007-02-01)
    Chen, Ming-Jer
    ;
    Yan, Shih-Guei
    ;
    Chen, Rong-Ting
    ;
    Hsieh, Chen-Yu
    ;
    Huang, Pin-Wei
    The MOSFET backscattering theory relies on a so-called "k(B)T" layer. In this letter, we adopt two different approaches to examine the temperature dependencies of the width spanned by this critical zone. First of all, a 55-nm channel length n-MOSFET is extensively characterized at three temperatures of 233 K, 263 K, and 298 K while undergoing a parameter decoupling/transformation process. A unique relationship is straightforwardly created and is comparable with that in the literature: The width of the "kBT" layer is proportional to the square root of temperature. The case of 77 K is also projected. Other corroborating evidence is a Monte Carlo particle simulation conducted on an 80-nm-long silicon conductor with the "kBT" layer's width proportional to the temperature in the high field region. Without adjusting any parameters, the backscattering theory is shown to work well for the demonstrated temperatures down to 77 K.
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    Measurement of channel stress using gate direct tunneling current in uniaxially stressed nMOSFETs
    (2007-09-01)
    Hsieh, Chen-Yu
    ;
    Chen, Ming-Jer
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    We measure the conduction-band electron direct tunneling current through the 1.27-nm gate oxide of nMOSFETs transistors that undergo longitudinal stress via a layout technique. With known process parameters and published deformation potential constants as input, fitting of the measured direct tunneling current versus gate voltage leads to the channel stress of around 0, -100, and -300 MPa for a gate-to-trench isolation spacing of 2.4, 0.495, and 0.21 mu m, respectively. To examine the accuracy of the method, a link with the mobility and threshold voltage measurements on the same device is conducted. The resulting piezoresistance coefficient and band offset are in good agreement with the literature values. The layout technique used is validated as well.
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    A constant-mobility method to enable MOSFET series-resistance extraction
    (2007-12-01)
    Lin, Da-Wen
    ;
    Cheng, Ming-Lung
    ;
    Wang, Shyh-Wei
    ;
    Wu, Chung-Cheng
    ;
    Chen, Ming-Jer
    A new method of extracting the MOSFET series resistance R-sd is proposed. This method requires only simple dc measurements on a single test device. Experimental demonstration is presented, without requiring quantities such as gate-oxide thickness, physical gate length, or effective channel length. The merit of the method stems from the specifically arranged bias conditions in which the channel carrier mobility remains constant for high vertical electric fields. It is this unique property which, makes the proposed method suitable for short-channel devices.
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    Electrical measurement of local stress and lateral diffusion near Source/Drain extension corner of uniaxially stressed n-MOSFETs
    (2008-03-01)
    Hsieh, Chen-Yu
    ;
    Chen, Ming-Jer
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    -On a 1.27-nm gate oxide n-MOSFET that undergoes longitudinal stress via a layout technique, subthreshold current is measured as a function of the gate edge to shallow-trench isolation (STI) spacing and is transformed via bandgap shift into the source/drain extension corner stress. The extracted local stress is quantitatively comparable with those of the channel as created by the gate direct tunneling measurement in inversion, the mobility measurement, and the threshold voltage measurement. In addition, its dependencies on the gate edge to STI spacing confirm the validity of the layout technique in controlling the corner or channel stress. The gate edge direct tunneling (EDT) measurement in accumulation straightforwardly leads to the quantified gate-to-source/drain-extension overlap length. Particularly, a retarded diffusion length of 1.1 nm for a stress change of -320 MPa and the resulting strain-induced activation energy both are in satisfactory agreement with those of the process simulation. A physically oriented analytic model is, therefore, reached, expressing the lateral diffusion as a function of the corner stress.
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    A parabolic potential barrier-oriented compact model for the kappa T-B layer's width in nano-MOSFETs
    (2008-05-01)
    Chen, Ming-Jer
    ;
    Lu, Li-Fang
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    On the basis of a parabolic potential profile around the source-channel junction barrier of nanoscale MOSFETs, a new compact model is physically derived, which links the width of thermal energy kappa T-B layer (a critical zone in the context of the backscattering theory) to the geometrical and bias parameters of the devices. The proposed model is supported by experimental data and by a critical analysis of various simulation works presented in the literature. The only fitting parameter remains constant in a wide range of channel length (10-65 nm), gate voltage (0.4-1.2 V), drain voltage (0.2-1.2 V), and temperature (100 K-500 K). The confusing temperature-dependent issues in the open literature are straightforwardly clarified.
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    A millisecond-anneal-assisted selective fully silicided (FUSI) gate process
    (2008-09-01)
    Lin, Da-Wen
    ;
    Wang, Maureen
    ;
    Cheng, Ming-Lung
    ;
    Sheu, Yi-Ming
    ;
    Tarng, Bennet
    We demonstrate, for the first time, an integration-friendly selective PMOSFET fully silicided (FUSI) gate process. In this process, a millisecond-anneal (NISA) technique is utilized for the nickel silicide phase transformation. A highly tensile FUSI gate electrode is created and hence exerts compressive stress in the underlying channel. The highly flexible integration scheme successfully, and exclusively, implements uniform P+ FUSI gates for PMOSFETs while preserving a FUSI-free N+ poly-Si gate for PMOSFETs with the feature size down to 30 run. A 20% improvement in FUSI-gated PMOSFET I-on-I-off is measured, which can be attributed to the enhanced hole mobility and the elimination of P+ poly-gate depletion.
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    On the Mean Free Path for Backscattering in k(B)T Layer of Bulk Nano-MOSFETs
    (2008-12-01)
    Chen, Ming-Jer
    ;
    Lu, Li-Fang
    ;
    Hsu, Chih-Yu
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    We perform Monte Carlo particle simulations on a silicon conductor for the purposes of reexamining the channel backscattering in bulk nano-MOSFETs. The resulting mean free path lambda(0) for backscattering in a long and near-equilibrium conductor is constant, regardless of the potential profile. However, the apparent mean free path lambda(1) in a local quasi-ballistic k(B)T layer depends on the curvature of the potential profile. In a linear potential profile, the lambda(1) extracted in a wide range of the conductor length (15 to 100 nm) and lattice temperature (150 to 300 K) is found to fall below lambda(0). The carrier heating as the origin of reduced mean free path is inferred from the simulated carrier velocity distribution near the injection point. Strikingly, the mean free paths in a parabolic potential profile remain consistent: lambda(1) = lambda(0) This indicates the absence or weakening of the carrier heating in the layer of interest, valid only for the parabolic potential barrier.