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A Model for Neutral Defect Limited Electron Mobility in Strained-Silicon Inversion Layers
(2017-03-01)
Hsieh, Shang-Hsun
;
Chen, Ming-Jer
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
On the strained silicon metal-oxide-semiconductor field-effect transistors (MOSFETs), we show how to derive a formalism dealing with the scattering of a 2-D electron by a neutral defect. The corresponding neutral defect limited inversion-layer electron mobility, mu(n), is calculated in the momentum relaxation time approximation. The calculated results lead to a new analytical model: mu(n) = cN(n)(-1) where N-n is the neutral defect density per unit area and c is the coefficient independent of the inversion-layer density, the strain, and the temperature. The validity and applicability of the model are confirmed by citing three independent experiments on strained silicon MOSFETs undergoing different implantation sources and different annealing budgets. Importantly, this paper clarifies for the first time that strain will not change neutral defect limited mobility unless changing the neutral defect density. This reasonably explains the two experimental observations during implantation and annealing: 1) the implantation-induced strain relaxation in strained sample does not occur and 2) the neutral defect density is much higher in strained sample than in unstrained sample.
Probing Long-Range Coulomb Interactions in Nanoscale MOSFETs
(2013-12-01)
Chen, Ming-Jer
;
Chang, Li-Ming
;
Wei, Sih-Yun
;
Chen, Wan-Li
;
Yeh, Ting-Hsien
We have recently experimentally probed long-range Coulomb interactions due to plasmons in polysilicon gate of long-channel (1 mu m) MOSFETs. In this letter, we further probe those due to plasmons in the highly doped source and drain. Test vehicles include four more samples from the same manufacturing process but with small channel lengths (down to 33 nm). I-V's of devices are measured at two drain voltages of 0.05 and 1 V, in a temperature range of 292-380 K. Inverse modeling technique is applied to furnish calibrated doping profiles. The inversion layer electron effective mobility is thereby extracted, showing a decreasing trend with decreasing channel length. Such differences reflect more additional scatterers in the shorter devices. Mobility components limited by these additional scatterers are assessed using Matthiessen's rule. From the extracted temperature dependencies, we infer that the strength of source/drain plasmons increases with decreasing channel length. The errors of Matthiessen's rule are adequately dealt with. Corroborative evidence is given as well.
Error-Free Matthiessen's Rule in the MOSFET Universal Mobility Region
(2013-02-01)
Chen, Ming-Jer
;
Lee, Wei-Han
;
Huang, Yi-Hui
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Through the experimentally validated inversion-layer mobility simulation, we devise an error-free version of Matthiessen's rule for a single-gate n-channel bulk MOSFET in the universal mobility region. The core of the new rule lies in a semi-empirical model, which explicitly expresses the errors due to the conventional use of Matthiessen's rule as a function of both the lowest subband population and the relative strength of individual mobility components. The model holds under practical conditions (with temperatures up to 400 K) and in a broad range of substrate doping concentrations (10(14) to 10(18) cm(-3)). To make the error-free proposal more general, we elaborate on several issues, including strain, impurity Coulomb scattering, and remote scattering. The thin-film case can be treated accordingly.
Effect of Strained k . p Deformation Potentials on Hole Inversion-Layer Mobility
(2013-04-01)
Chen, Ming-Jer
;
Lee, Chien-Chih
;
Chen, Wan-Li
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In the literature dedicated to strained p-type metal-oxide-semiconductor field-effect transistor inversion-layer mobility calculation via a k . p valence-band structure, three key strain-related material parameters, namely, the Bir-Pikus deformation potentials a(upsilon), b, and d, were widespread in magnitude. To improve such large discrepancies, in this paper, we conduct sophisticated calculations on < 110 >/(001) and < 110 >/(110) hole inversion-layer mobility for gigapascal-level uniaxial stresses along each of three crystallographic directions. The screening effect on surface roughness scattering is taken into account. We find that, to affect the calculated hole mobility enhancement, a(upsilon) is weak, b is moderate, and d is strong, particularly for the uniaxial compressive stress along the < 110 > direction. This provides experimental guidelines for an optimal determination of the primary factor, i.e., d, and the secondary factor, i.e., b, with the commonly used values for a(upsilon). The result remains valid for varying surface roughness parameters and models and is supported by recent first-principles and tight-binding calculations. Thus, the strained k . p valence-band structure with the optimized deformation potentials can ensure the accuracy of the calculated transport properties of 2-D hole gas under stress.
Evidence for the Fourfold-Valley Confinement Electron Piezo-Effective-Mass Coefficient in Inversion Layers of < 110 > Uniaxial-Tensile-Strained (001) nMOSFETs
(2012-06-01)
Chen, Ming-Jer
;
Lee, Wei-Han
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We have recently experimentally extracted the piezo-effective-mass coefficients of 2-D electrons via the gate tunneling current of (001) n-channel metal-oxide-semiconductor field-effect transistors under < 110 > uniaxial compressive stress. The results pointed to the existence of a piezo-effective-mass coefficient around the fourfold conduction-band valley in the out-of-plane (quantum confinement) direction. To strengthen this further, here, we provide extra evidence. First, explicit guidelines are drawn to distinguish all the piezo-effective-mass coefficients. Then, a self-consistent strain quantum simulation is executed to fit literature data of both the mobility enhancement and gate current suppression in the uniaxial tensile stress situation. It is found that neglecting the fourfold-valley out-of-plane piezo-effective-mass coefficient, as in existing band structure calculations, only leads to a poor fitting.
Temperature-Oriented Mobility Measurement and Simulation to Assess Surface Roughness in Ultrathin-Gate-Oxide (similar to 1 nm) nMOSFETs and Its TEM Evidence
(2012-04-01)
Chen, Ming-Jer
;
Chang, Li-Ming
;
Kuang, Shin-Jiun
;
Lee, Chih-Wei
;
Hsieh, Shang-Hsun
On a 1.27-nm gate-oxide nMOSFET, we make a comprehensive study of SiO2/Si interface roughness by combining temperature-dependent electron mobility measurement, sophisticated mobility simulation, and high-resolution transmission electron microscopy (TEM) measurement. Mobility measurement and simulation adequately extract the correlation length lambda and roughness rms height Delta of the sample, taking into account the Coulomb-drag-limited mobilities in the literature. The TEM measurement yields the apparent correlation length lambda(m) and roughness rms height Delta(m). It is found that the following hold: 1) lambda approximate to lambda(m) for both the Gaussian and exponential models, validating the temperature-oriented extraction process; 2) the extracted Delta (similar to 1.3 angstrom for the Gaussian model and 1.0 angstrom for the exponential one) is close to that (similar to 1.2 angstrom) of Delta(m), all far less than the conventional values (similar to 3 angstrom) in thick-gate-oxide case; and 3) the TEM 2-D projection correction coefficient Delta(m)/Delta is approximately 1.0, which cannot be elucidated with the current thick-gate-oxide-based knowledge.
A constant-mobility method to enable MOSFET series-resistance extraction
(2007-12-01)
Lin, Da-Wen
;
Cheng, Ming-Lung
;
Wang, Shyh-Wei
;
Wu, Chung-Cheng
;
Chen, Ming-Jer
A new method of extracting the MOSFET series resistance R-sd is proposed. This method requires only simple dc measurements on a single test device. Experimental demonstration is presented, without requiring quantities such as gate-oxide thickness, physical gate length, or effective channel length. The merit of the method stems from the specifically arranged bias conditions in which the channel carrier mobility remains constant for high vertical electric fields. It is this unique property which, makes the proposed method suitable for short-channel devices.
Temperature-Dependent Remote-Coulomb-Limited Electron Mobility in n(+)-Polysilicon Ultrathin Gate Oxide nMOSFETs
(2011-04-01)
Chen, Ming-Jer
;
Chang, Sou-Chi
;
Kuang, Shin-Jiun
;
Lee, Chien-Chih
;
Lee, Wei-Han
Additional electron mobility due to remote scatterers in n(+)-polysilicon 1.65-nm gate oxide (SiO(2)) n-channel metal-oxide-semiconductor field-effect transistors is experimentally extracted at three different temperatures (i.e., 233, 263, and 298 K). The core of the extraction process consists of simulated temperature-dependent universal mobility curves and Matthiessen's rule in a mobility universality region. Resulting additional mobility for the first time experimentally exhibits a negative temperature coefficient, confirming interface plasmons in a polysilicon depletion region to be dominant remote Coulomb scatterers. We also present corroborative evidence as quoted in the literature, including: 1) calculated temperature-dependent remote Coulomb mobility due to ionized impurity atoms in a polysilicon depletion region; 2) experimentally assessed additional mobility at room temperature; and 3) simulated remote Coulomb mobility due to interface plasmons in a polysilicon depletion region as well as its temperature coefficient. Validity of Matthiessen's rule used in this paper is verified.

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