學術出版;;Publications

Permanent URI for this communityhdl:11536/1

收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

Browse

🏛️國立陽明交通大學機構典藏

Search Results

Now showing 1 - 8 of 8

A Model for Neutral Defect Limited Electron Mobility in Strained-Silicon Inversion Layers
(2017-03-01)
Hsieh, Shang-Hsun
;
Chen, Ming-Jer
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
On the strained silicon metal-oxide-semiconductor field-effect transistors (MOSFETs), we show how to derive a formalism dealing with the scattering of a 2-D electron by a neutral defect. The corresponding neutral defect limited inversion-layer electron mobility, mu(n), is calculated in the momentum relaxation time approximation. The calculated results lead to a new analytical model: mu(n) = cN(n)(-1) where N-n is the neutral defect density per unit area and c is the coefficient independent of the inversion-layer density, the strain, and the temperature. The validity and applicability of the model are confirmed by citing three independent experiments on strained silicon MOSFETs undergoing different implantation sources and different annealing budgets. Importantly, this paper clarifies for the first time that strain will not change neutral defect limited mobility unless changing the neutral defect density. This reasonably explains the two experimental observations during implantation and annealing: 1) the implantation-induced strain relaxation in strained sample does not occur and 2) the neutral defect density is much higher in strained sample than in unstrained sample.
An Extreme Surface Proximity Push for Embedded SiGe in pMOSFETs Featuring Self-Aligned Silicon Reflow
(2010-09-01)
Lin, Da-Wen
;
Chen, Chien-Liang
;
Chen, Ming-Jer
;
Wu, Chung-Cheng
;
電子工程學系及電子研究所
This letter proposes a novel process to modulate the distance, or proximity, between the tip of embedded silicon-germanium (e-SiGe) and the channel region in pMOSFETs. Traditionally, sophisticated etching treatment is adopted in a spacer structure; however, process-induced variation in the e-SiGe proximity may lead to serious variation in pMOSFET performance. In this letter, an extremely close proximity is achieved using self-aligned silicon reflow (SASR) in hydrogen ambient. As opposed to conventional approaches which have e-SiGe proximity determined by spacer width, the tip of e-SiGe with SASR can be positioned flush with the gate edge, as corroborated by both the TEM analyses and TCAD simulation. A significant improvement in pMOSFET performance is also measured.
Error-Free Matthiessen's Rule in the MOSFET Universal Mobility Region
(2013-02-01)
Chen, Ming-Jer
;
Lee, Wei-Han
;
Huang, Yi-Hui
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Through the experimentally validated inversion-layer mobility simulation, we devise an error-free version of Matthiessen's rule for a single-gate n-channel bulk MOSFET in the universal mobility region. The core of the new rule lies in a semi-empirical model, which explicitly expresses the errors due to the conventional use of Matthiessen's rule as a function of both the lowest subband population and the relative strength of individual mobility components. The model holds under practical conditions (with temperatures up to 400 K) and in a broad range of substrate doping concentrations (10(14) to 10(18) cm(-3)). To make the error-free proposal more general, we elaborate on several issues, including strain, impurity Coulomb scattering, and remote scattering. The thin-film case can be treated accordingly.
Effect of Strained k . p Deformation Potentials on Hole Inversion-Layer Mobility
(2013-04-01)
Chen, Ming-Jer
;
Lee, Chien-Chih
;
Chen, Wan-Li
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In the literature dedicated to strained p-type metal-oxide-semiconductor field-effect transistor inversion-layer mobility calculation via a k . p valence-band structure, three key strain-related material parameters, namely, the Bir-Pikus deformation potentials a(upsilon), b, and d, were widespread in magnitude. To improve such large discrepancies, in this paper, we conduct sophisticated calculations on < 110 >/(001) and < 110 >/(110) hole inversion-layer mobility for gigapascal-level uniaxial stresses along each of three crystallographic directions. The screening effect on surface roughness scattering is taken into account. We find that, to affect the calculated hole mobility enhancement, a(upsilon) is weak, b is moderate, and d is strong, particularly for the uniaxial compressive stress along the < 110 > direction. This provides experimental guidelines for an optimal determination of the primary factor, i.e., d, and the secondary factor, i.e., b, with the commonly used values for a(upsilon). The result remains valid for varying surface roughness parameters and models and is supported by recent first-principles and tight-binding calculations. Thus, the strained k . p valence-band structure with the optimized deformation potentials can ensure the accuracy of the calculated transport properties of 2-D hole gas under stress.
Evidence for the Fourfold-Valley Confinement Electron Piezo-Effective-Mass Coefficient in Inversion Layers of < 110 > Uniaxial-Tensile-Strained (001) nMOSFETs
(2012-06-01)
Chen, Ming-Jer
;
Lee, Wei-Han
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We have recently experimentally extracted the piezo-effective-mass coefficients of 2-D electrons via the gate tunneling current of (001) n-channel metal-oxide-semiconductor field-effect transistors under < 110 > uniaxial compressive stress. The results pointed to the existence of a piezo-effective-mass coefficient around the fourfold conduction-band valley in the out-of-plane (quantum confinement) direction. To strengthen this further, here, we provide extra evidence. First, explicit guidelines are drawn to distinguish all the piezo-effective-mass coefficients. Then, a self-consistent strain quantum simulation is executed to fit literature data of both the mobility enhancement and gate current suppression in the uniaxial tensile stress situation. It is found that neglecting the fourfold-valley out-of-plane piezo-effective-mass coefficient, as in existing band structure calculations, only leads to a poor fitting.
Reproducing subthreshold characteristics of metal-oxide-semiconductor field effect transistors under shallow trench isolation mechanical stress using a stress-dependent diffusion model
(2006-08-01)
Sheu, Yi-Ming
;
Yang, Sheng-Jier
;
Wang, Chih-Chiang
;
Chang, Chih-Sheng
;
Chen, Ming-Jer
N-channel metal-oxide-semiconductor field effect transistors (MOSFETs) with a lightly doped well exhibit subthreshold current versus voltage (I-V) characteristics that are sensitive to shallow trench isolation (STI) mechanical stress. Such striking dependencies offer the opportunity to validate a proposed two-dimensional (2D) process model that relates the impurity diffusion to the mechanical stress throughout the substrate. With the assistance of sophisticated process/device simulations, the model appears to satisfactorily reproduce subthreshold I-V characteristics for different active area lengths and different substrate biases. The stress-dependent point defect equilibrium concentration and diffusion model are also implemented to evaluate the stress effect on transient enhanced diffusion.
Measurement of channel stress using gate direct tunneling current in uniaxially stressed nMOSFETs
(2007-09-01)
Hsieh, Chen-Yu
;
Chen, Ming-Jer
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We measure the conduction-band electron direct tunneling current through the 1.27-nm gate oxide of nMOSFETs transistors that undergo longitudinal stress via a layout technique. With known process parameters and published deformation potential constants as input, fitting of the measured direct tunneling current versus gate voltage leads to the channel stress of around 0, -100, and -300 MPa for a gate-to-trench isolation spacing of 2.4, 0.495, and 0.21 mu m, respectively. To examine the accuracy of the method, a link with the mobility and threshold voltage measurements on the same device is conducted. The resulting piezoresistance coefficient and band offset are in good agreement with the literature values. The layout technique used is validated as well.
Electrical measurement of local stress and lateral diffusion near Source/Drain extension corner of uniaxially stressed n-MOSFETs
(2008-03-01)
Hsieh, Chen-Yu
;
Chen, Ming-Jer
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
-On a 1.27-nm gate oxide n-MOSFET that undergoes longitudinal stress via a layout technique, subthreshold current is measured as a function of the gate edge to shallow-trench isolation (STI) spacing and is transformed via bandgap shift into the source/drain extension corner stress. The extracted local stress is quantitatively comparable with those of the channel as created by the gate direct tunneling measurement in inversion, the mobility measurement, and the threshold voltage measurement. In addition, its dependencies on the gate edge to STI spacing confirm the validity of the layout technique in controlling the corner or channel stress. The gate edge direct tunneling (EDT) measurement in accumulation straightforwardly leads to the quantified gate-to-source/drain-extension overlap length. Particularly, a retarded diffusion length of 1.1 nm for a stress change of -320 MPa and the resulting strain-induced activation energy both are in satisfactory agreement with those of the process simulation. A physically oriented analytic model is, therefore, reached, expressing the lateral diffusion as a function of the corner stress.

學術出版;;Publications

Browse

Filters

Settings

Sort By

Results per page

🏛️國立陽明交通大學機構典藏

Search Results