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Gate Direct Tunneling Current in Uniaxially Compressive Strained nMOSFETs: A Sensitive Measure of Electron Piezo Effective Mass
(2011-01-01)
Lee, Wei-Han
;
Chen, Ming-Jer
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Currently, both the band-structure calculation and the mobility measurement are used to assess the electron piezo-effective-mass coefficients in strained nMOSFETs. In this paper, we present a new experimental method through a fitting of the strain-altered electron gate direct tunneling current. The core of this method lies in the sensitivity of the direct tunneling to the position of the subband level in the presence of the electron piezo-effective-mass coefficients. First, a correction-coefficient generating expression is systematically constructed to compensate for the error in the subband levels due to the use of a triangular potential approximation. Then, with the known deformation potential constants and uniaxially compressive stress in the channel as inputs, a strain quantum simulator is carried out. The resulting gate direct tunneling current is used to fit experimental data, thus leading to the values of the piezo-effective-mass coefficients associated with the twofold and fourfold valleys. The comparison of the extracted piezo-effective-mass coefficients to those published in the literature is made.
Evidence for the Fourfold-Valley Confinement Electron Piezo-Effective-Mass Coefficient in Inversion Layers of < 110 > Uniaxial-Tensile-Strained (001) nMOSFETs
(2012-06-01)
Chen, Ming-Jer
;
Lee, Wei-Han
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We have recently experimentally extracted the piezo-effective-mass coefficients of 2-D electrons via the gate tunneling current of (001) n-channel metal-oxide-semiconductor field-effect transistors under < 110 > uniaxial compressive stress. The results pointed to the existence of a piezo-effective-mass coefficient around the fourfold conduction-band valley in the out-of-plane (quantum confinement) direction. To strengthen this further, here, we provide extra evidence. First, explicit guidelines are drawn to distinguish all the piezo-effective-mass coefficients. Then, a self-consistent strain quantum simulation is executed to fit literature data of both the mobility enhancement and gate current suppression in the uniaxial tensile stress situation. It is found that neglecting the fourfold-valley out-of-plane piezo-effective-mass coefficient, as in existing band structure calculations, only leads to a poor fitting.
Evidence for a Very Small Tunneling Effective Mass (0.03m(0)) in MOSFET High-k (HfSiON) Gate Dielectrics
(2012-04-01)
Chen, Ming-Jer
;
Hsu, Chih-Yu
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We have recently conducted experimental and modeling tasks on TaC/HfSiON/SiON n-type MOSFETs, leading to an effective mass of 0.03m(0) for 2-D electrons tunneling in high-k HfSiON dielectrics. In this letter, we present extra evidence obtained from complementary MOSFETs undergoing the same TaC/HfSiON/SiON processing, which shows that such a very small tunneling effective mass is existent not only for 3-D electrons but also for 2-D holes. This new finding is very important because it can substantially enhance the current understanding of gate tunneling leakage suppression in metal-gate high-k MOSFETs.
Measurement of channel stress using gate direct tunneling current in uniaxially stressed nMOSFETs
(2007-09-01)
Hsieh, Chen-Yu
;
Chen, Ming-Jer
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We measure the conduction-band electron direct tunneling current through the 1.27-nm gate oxide of nMOSFETs transistors that undergo longitudinal stress via a layout technique. With known process parameters and published deformation potential constants as input, fitting of the measured direct tunneling current versus gate voltage leads to the channel stress of around 0, -100, and -300 MPa for a gate-to-trench isolation spacing of 2.4, 0.495, and 0.21 mu m, respectively. To examine the accuracy of the method, a link with the mobility and threshold voltage measurements on the same device is conducted. The resulting piezoresistance coefficient and band offset are in good agreement with the literature values. The layout technique used is validated as well.
Electrical measurement of local stress and lateral diffusion near Source/Drain extension corner of uniaxially stressed n-MOSFETs
(2008-03-01)
Hsieh, Chen-Yu
;
Chen, Ming-Jer
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
-On a 1.27-nm gate oxide n-MOSFET that undergoes longitudinal stress via a layout technique, subthreshold current is measured as a function of the gate edge to shallow-trench isolation (STI) spacing and is transformed via bandgap shift into the source/drain extension corner stress. The extracted local stress is quantitatively comparable with those of the channel as created by the gate direct tunneling measurement in inversion, the mobility measurement, and the threshold voltage measurement. In addition, its dependencies on the gate edge to STI spacing confirm the validity of the layout technique in controlling the corner or channel stress. The gate edge direct tunneling (EDT) measurement in accumulation straightforwardly leads to the quantified gate-to-source/drain-extension overlap length. Particularly, a retarded diffusion length of 1.1 nm for a stress change of -320 MPa and the resulting strain-induced activation energy both are in satisfactory agreement with those of the process simulation. A physically oriented analytic model is, therefore, reached, expressing the lateral diffusion as a function of the corner stress.
A Method of Extracting Metal-Gate High-k Material Parameters Featuring Electron Gate Tunneling Current Transition
(2011-04-01)
Hsu, Chih-Yu
;
Chang, Hua-Gang
;
Chen, Ming-Jer
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
For metal-gate high-k dielectrics, there is a transition region in the electron gate tunneling current I(g), as characterized by a plot of dlnI(g)/dV(g) versus V(g). In this paper, we systematically construct a new fitting over the region, which can accurately determine material parameters, including metal work function, high-k electron affinity, and tunneling effective masses of electrons. First of all, a calculation of gate current due to electron direct tunneling and/or Fowler-Nordheim tunneling from an inversion layer is performed, yielding the guidelines of the fitting. Experimental samples are presented with n-channel metal-oxide-semiconductor field-effect transistors having low effective oxide thickness (1.4 nm) TaC/HfSiON/SiON gate stacks. Underlying material parameters are extracted accordingly and remain valid for higher temperature and gate voltage. We also demonstrate that a conventional method without a dlnI(g)/dV(g) fitting might lead to erroneous results. Thus, the dlnI(g)/dV(g) fitting is crucial to metal-gate high-k material parameter assessment.
Distinguishing Between STI Stress and Delta Width in Gate Direct Tunneling Current of Narrow n-MOSFETs
(2009-05-01)
Hsieh, Chen-Yu
;
Lin, Yi-Tang
;
Chen, Ming-Jer
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Direct tunneling current across a 1.27-nm-thick gate oxide of n-MOSFETs under STI compressive stress is measured in a wide range of the drawn gate width W (= 0.11, 0.24, 0.6, 1.0 and 10 mu m). The apparent gate current per unit width exhibits an increasing trend with decreasing W. In this narrowing direction, two fundamentally different effects are encountered: one of the delta width (Delta W) near the STI edge, and the other of the enhanced STI stress in the channel. To distinguish between the two effects, a new analytical width-dependent direct tunneling model is developed and applied. Reasonable agreement with data is achieved. The resulting delta width effect is found to dominate over the stress effect in narrow devices, while for the wide ones, they are comparable. The extracted Delta W (similar to 63 nm) and the underlying channel stress (with the uncertainties identified) straightforwardly produce a good fitting of the drain current variation counterpart. Specifically, it is justified that the delta width and STI stress are cooperative in constituting gate current variation, but both have opposite effects on the drain current one.
Enhanced Hole Gate Direct Tunneling Current in Process-Induced Uniaxial Compressive Stress p-MOSFETs
(2009-08-01)
Hsu, Chih-Yu
;
Lee, Chien-Chih
;
Lin, Yi-Tang
;
Hsieh, Chen-Yu
;
Chen, Ming-Jer
On a nominally 1.27-nm-thick gate oxide p-MOSFET with shallow trench isolation (STI) longitudinal compressive mechanical stress, hole gate direct tunneling current in inversion is measured across the wafer. The resulting average gate current exhibits an increasing trend with STI compressive stress. However, this is exactly contrary to the currently recognized trend: hole gate direct tunneling current decreases with externally applied compressive stress, which is due to the strain-altered valence-band splitting. To determine the mechanisms responsible, a quantum strain simulator is established, and its validity is confirmed. The simulator then systematically leads us to the finding of the origin: a reduction in the physical gate oxide thickness, with the accuracy identified down to 0.001 nm, occurs under the influence of the STI compressive stress. The strain-retarded oxide growth rate can significantly enhance hole direct tunneling and thereby reverse the conventional trend due to the strain-altered valence-band splitting.

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