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Now showing 1 - 10 of 36

A 69.3% Efficiency, 6.78-MHz Wireless Power Delivery System with 0X/1X Regulating Rectifier and Reconfigurable Power Amplifier
(2019-01-01)
Fuh, Jonathan
;
Yang, Fu-Bin
;
Chen, Po-Hung
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we present a 6.78-MHz highefficiency wireless power transfer system with a reconfigurable class-D power amplifier and a 0X/1X regulating rectifier. The proposed reconfigurable power amplifier delivers 0.25X/1X output power by adjusting the power-stage configuration to improve system efficiency. To enhance the receiver efficiency, the proposed 0X/1X regulating rectifier with adaptive offset compensation achieves both voltage rectification and voltage regulation in a single conversion stage. The measurement results demonstrate a 90.1% peak receiver efficiency and a 69.3% peak system efficiency. The system provides the load circuit with 5-V regulated output and 250-mW maximum output power.
A Fully Integrated Step-Down Switched-Capacitor DC-DC Converter With Dual Output Regulation Mechanisms
(2020-09-01)
Chen, Po-Han
;
Cheng, Hao-Chung
;
Chen, Po-Hung
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This letter proposes a fully integrated step-down switched-capacitor (SC) DC-DC converter using 0.18-mu m CMOS technology for system-on-chip applications. The proposed stepdown switched-capacitor DC-DC converter used two control mechanisms: the switch array modulation technique to regulate the output voltage and the voltage ripple modulation technique to adjust the output voltage ripple of the converter as the loading current varied. As a result, the proposed converter could generate a regulated output voltage with low voltage ripple. The converter core performed at conversion ratios of 1/3 and 1/2 under an input voltage of 1.8 V. The measurement results on 180-nm technology showed that the proposed fully integrated step-down switched-capacitor DC-DC converter could achieve a peak power conversion efficiency of 74.1% and maintain power conversion efficiency at levels over 70% within loading ranges between 1.4 and 5 mA. The output voltage ripple was controlled at levels under 63.4 mV within a loading current ranging between 0.1 and 5 mA.
A Fully Integrated Light-Powering System with Integrated CMOS Photovoltaic Cell for Batteryless IoT Devices
(2019-01-01)
Chen, Po-Han
;
Huang, Chao-Yi
;
Cheng, Hao-Chung
;
Chen, Po-Hung
;
電子工程學系及電子研究所
This paper presents a fully integrated CMOS lightpowering system, integrating CMOS photovoltaic cell and energy harvesting interface, for batteryless internet of things (IoT). The CMOS photovoltaic cell employs deep N-well (DNW) based structure to improve the light-electric conversion efficiency. The energy harvesting interface utilizes a fully integrated two-stage switched-capacitor dc-dc converter to provide an appropriate output voltage for load circuits. It provides 1 V and 0.9 - 1.1 V output under light load and heavy load, respectively. The chip is designed and fabricated by 180-nm CMOS process, without using any off-chip components, except a storage capacitor for testing. The experimental results demonstrate that the proposed 1mm x 2mm fully integrated light-powering system can periodically provide 0.9 V to 1.1 V output voltage to power 1-mA loading circuit. The proposed interface achieves 70 percent peak-efficiency at 1 mu A and higher than 60 percent efficiency over 0.5 mu A to 2 mu A loading currents.
Improved Charge Pump Design and Ex Vivo Experimental Validation of CMOS 256-Pixel Photovoltaic-Powered Subretinal Prosthetic Chip
(2020-05-01)
Kuo, Po-Han
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Wong, Oi-Ying
;
Tzeng, Chi-Kuan
;
Wu, Pu-Wei
;
Chiao, Chuan-Chin
An improved design of CMOS 256-pixel photovoltaic-powered implantable chip for subretinal prostheses is presented. In the proposed subretinal chip, a high-efficiency fully-integrated 4x charge pump is designed and integrated with on-chip photovoltaic (PV) cells and a 256-pixel array with active pixel sensors (APS) for image light sensing, biphasic constant current stimulators, and electrodes. Thus the PV voltage generated by infrared (IR) light can be boosted to above 1V so that the charge injection is increased. The proposed chip adopts the 32-phase divisional power supply scheme (DPSS) to reduce the required supply current and thus the required area of the PV cells. The proposed chip is designed and fabricated in 180-nm CMOS image sensor (CIS) technology and post-processed with biocompatible IrOx electrodes and silicone packaging. From the electrical measurement results, the measured stimulation frequency is 28.3 Hz under the equivalent electrode impedance load. The measured maximum output stimulation current is 7.1 mu A and the amount of injected charges per pixel is 7.36 nC under image light intensity of 3200 lux and IR light intensity of 100 mW/cm(2). The function of the proposed chip has been further validated successfully with the ex vivo experimental results by recording the electrophysiological responses of retinal ganglion cells (RGCs) of retinas from retinal degeneration (rd1) mice with a multi-electrode array (MEA). The measured average threshold injected charge is about 3.97 nC which is consistent with that obtained from the patch clamp recording on retinas from wild type (C57BL/6) mice with a single electrode pair.
Single-Inductor Dual-Input Dual-Output Battery-PV Hybrid System With 2-D Adaptive On-Time Control for Internet of Things
(2020-03-01)
Lee, Hui-Hsuan
;
Liu, Chi-Wei
;
Takamiya, Makoto
;
Chen, Po-Hung
;
電子工程學系及電子研究所
In this article, we present a single-inductor dual-input dual-output power converter with two-dimensional adaptive-on-time (2-D AOT) control for Internet of things (IoT) applications. The proposed system combines energy from a 0.55-0.7 V photovoltaic (PV) module with a non-rechargeable 1.4-V zinc-air battery to extend the battery life. The proposed converter employs the buck-boost mode and the buck mode for the PV module and the battery, respectively, to produce two output voltages for different loading currents. The proposed 2-D AOT technique not only reduces the output voltage ripple but also improves the dual-source conversion efficiency over a wide input voltage range. Moreover, the response time of the self-tracking zero-current detector can also be improved by the proposed 2-D AOT. We fabricated the test chip using 0.18-mu m technology in an area of 1.9 x 2.2 mm(2). The measurement results demonstrated a peak efficiency of 92.5% with an input voltage range of 0.55-1.4 V. The output voltage ripple was less than 2.3% VOUT under different input voltage ranges.
A Single-Inductor Triple-Source Quad-Mode Energy-Harvesting Interface With Automatic Source Selection and Reversely Polarized Energy Recycling
(2019-10-01)
Chen, Po-Hung
;
Cheng, Hao-Chung
;
Lo, Chih-Lun
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a single-inductor triple-source quad-mode (SITSQM) energy-harvesting interface in a 0.18-mu m CMOS process. The proposed reversely polarized energy recycling (RPER) technique improves not only the conversion efficiency at low input voltage but also the system's output power range. The interface employs the buck-boost topology to convert energy from photovoltaic (PV) cells and a thermoelectric generator (TEG) to a regulated 1.2-V output. The proposed converter features four different operating modes, namely, harvesting, recycling, storing, and backup. The operating mode is automatically selected according to the input and load conditions using the automatic source selection mechanism. The experimental results demonstrate 25.3% efficiency improvement and 10x output power range extension from the proposed RPER technique. The proposed SITSQM converter automatically manages three harvesting sources with 82.1% peak conversion efficiency.
An Optically-Powered 432 MHz Wireless Tag for Batteryless Internet-of-Things Applications
(2019-09-01)
Cheng, Hao-Chung
;
Chen, Yen-Ting
;
Chen, Po-Hung
;
Liao, Yu-Te
;
電子工程學系及電子研究所
This paper presents an optically-powered wireless tag, integrating a charge pump (CP) and a low-power RF transmitter for batteryless Internet-of-Things (IoT) applications. The proposed charge pump with hysteresis regulation mechanism (HRM) powers the transmitter circuit using indoor light energy. The charge pump enables the transmitter whenever the output capacitor stores sufficient energy and guarantees a short period signal transmission. The proposed low-power transmitter contains the subharmonically injection-locked PLL and the capacitive coupling technique to achieve a large frequency multiplication ratio. The proposed batteryless wireless chip is fabricated in 0.18-mu m CMOS process. The measurement results demonstrate that the proposed charge pump provides a 1.1 to 1.3 V hysteresis regulated voltage under indoor light illumination larger than 300 lux. The charge pump achieves 84.1% peak efficiency and the communication distance of 3 meters is demonstrated while only consuming 248 mu W.
An 82.9%-Efficiency Triple-Output Battery Management Unit for Implantable Neuron Stimulator in 180-nm Standard CMOS
(2019-05-01)
Liu, Chi-Wei
;
Chen, Yi-Lun
;
Liao, Pei-Chun
;
Lin, Shiau-Pin
;
Wang, Ting-Wei
This brief presents a high-efficiency battery management unit combining a single-inductor dual-output (SIDO) buck converter with two charge pumps (CPs) to provide three voltage levels (6 V, -6 V, and 2 V) for neuron stimulators in implantable medical devices. The stacked power stage in the buck converter mitigates the voltage stress issue in the power stage to manage 3.2-4.8 V battery voltage. By cascading a buck converter and CPs, the voltage across the CP power stage is reduced to generate 6 V and -6 V high voltage outputs without using high voltage devices. As a result, the proposed battery management could provide 6 V, -6 V, and 2 V output voltages from 3.2 to 4.8 V input voltage using a 180-nm standard CMOS process. The measurement results demonstrate that the proposed battery management achieved a peak efficiency of 82.9% with an available input voltage of 3.2-4.8 V.
An 82.1%-Power-Efficiency Single-Inductor Triple-Source Quad-Mode Energy Harvesting Interface with Automatic Source Selection and Reversely Polarized Energy Recycling
(2018-01-01)
Lo, Chih-Lun
;
Cheng, Hao-Chung
;
Liao, Pei-Chun
;
Chen, Yi-Lun
;
Chen, Po-Hung
In this paper, a single-inductor triple-source quad mode energy harvesting interface with automatic source selection is developed for multi-source energy harvesting. The interface employs buck-boost topology to convert the energy from photovoltaic (PV) cells and thermoelectric generator (TEG) to a regulated 1.2-V output. The proposed converter has four operating modes: harvesting mode (BM), recycling, mode (RM), storage mode (SM), and backup mode (BM). The operating mode is selected automatically according to the input and load conditions to appropriately transfer the energy. The proposed reversely polarized energy recycling (RPER) technique extends the available output power range by 10x with 25.3% efficiency improvement at low input voltage. The measurement results demonstrates the proposed interface achieves the peak efficiency of 82.1%.
A 13.56MHz Wireless Power Transfer System with Dual-Output Regulated Active Rectifier for Implantable Medical Devices
(2018-01-01)
Yang, Fu-Bin
;
Fuh, Jonathan
;
Chen, Po-Hung
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a 13.56 MHz wireless power transfer system with dual-output regulated active rectifier is developed for implantable medical devices. The rectifier employs pulse-skip modulation (PSM) to regulate two output voltages without using power consuming low dropout regulators (LDOs). The proposed automatic digital offset compensation adjusts both turn-on timing and turn-off timing to compensate the turn-on and turn-off delays of the comparator. The simulation results show that the proposed active rectifier achieves 94% efficiency. The entire wireless power transmission system including power amplifier, resonant tanks, and rectifier, has 67.2% maximum power conversion efficiency (PCE). Compared to the conventional approach with ideal LDOs, 19.2% efficiency improvement is obtained.

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