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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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Author: search.filters.author.Chen, Sau-GeeSubject: search.filters.subject.LDPC code

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Now showing 1 - 3 of 3
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    A systematic optimized comparison algorithm for fast LDPC decoding
    (2007)
    Hung, Jui-Hui
    ;
    Chen, Sau-Gee
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This paper proposes a novel systematic optimization algorithm for comparison operations required by a check node unit (CNU) in LDPC decoding, given any input number N-in. The algorithm can automatically synthesize an optimized fast comparison operations that guarantees a shortest comparison delay time of [log(2) (N-in - 1)] T-cmp and a minimized total number of two-input comparators, where T-cmp is the delay time of a comparator. High speed is achieved by adopting parallel divide-and-conquer comparison operations, while the required comparators are minimized by developing a novel set construction algorithm that maximizes shareable comparison operations. The designed CNU is favourable to the existing CNU designs which are non-systematically designed with either longer critical path delays or higher comparator counts than the proposed designs. The proposed design is particularly good for long code length cases, when it is impractical to do customized optimized designs by hand, due to high design complexity.
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    A 1.45Gb/s (576,288) LDPC decoder for 802.16e standard
    (2007)
    Hung, Jui-Hui
    ;
    Chen, Sau-Gee
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    In this work, a (576,288) LDPC decoder for 802.16e standard is presented. This design is a partially parallel architecture based on a new optimally reordered decoding scheme. Besides, the proposed architecture handles two different code words at a time to achieve 100% utilization rate of both CNU and BNU. As a result, high throughput and low hardware complexity are achieved. In chip implementation, the proposed design achieves a data rate of 1.45Gb/s with 10 iterations and 7 quantization bits, at the cost of 881K gates, based on UMC 0.18 mu m process technology.
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    An Efficient BF LDPC Decoding Algorithm Based on A Syndrome Vote Scheme
    (2008)
    Hung, Jui-Hui
    ;
    Chen, Sau-Gee
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This work presents a high-performance bit-flipping (BF) algorithm utilizing a proposed syndrome vote technique of a defined culprit bit set, named CVBF algorithm for LDPC decoding. It can achieve significant decoding performance improvements by about 0.9dB over the most efficient BF algorithm, owing to the introduced an additional syndrome vote procedure after updating the flipping reliabilities of all the received bits in each iteration. Moreover, its performance is comparable to the min-sum algorithm (MSA) under the condition of same iteration number, but with much lower complexity per iteration. The proposed syndrome vote scheme only costs little overhead in hardware realization. Besides, an early termination strategy suited for the proposed algorithm is also devised to further reduce the iteration number.