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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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Author: search.filters.author.Chen, Shih-HungSubject: search.filters.subject.Electrostatic discharge (ESD)

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Now showing 1 - 4 of 4
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    Active ESD Protection Design for Interface Circuits Between Separated Power Domains Against Cross-Power-Domain ESD Stresses
    (2008-09-01)
    Chen, Shih-Hung
    ;
    Ker, Ming-Dou
    ;
    Hung, Hsiang-Pin
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    Several complex electrostatic discharge (ESD) failure mechanisms have been found in the interface circuits of an IC product with multiple separated power domains. In this case, the machine-model (MM) ESD robustness cannot achieve 150 V in this IC product with separated power domains, although it can pass the 2-kV human-body-model (HBM) ESD test. The negative-to-VDD (ND) mode MM ESD currents were discharged by circuitous current paths through interface circuits to cause the gate oxide damage, the junction filament, and the contact destruction of the internal transistors. The detailed discharging paths of ND-mode ESD failures were analyzed in this paper. In addition, some ESD protection designs have been illustrated and reviewed to further comprehend the protection strategies for cross-power-domain ESD events. Moreover, one new active ESD protection design for the interface circuits between separated power domains has been proposed and successfully verified in a 0.13-mu m CMOS technology. The HBM and MM ESD robustness of the separated-power-domain interface circuits with the proposed active ESD protection design can achieve over 4 kV and 400 V, respectively.
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    Local CDM ESD Protection Circuits for Cross-Power Domains in 3D IC Applications
    (2014-06-01)
    Chen, Shih-Hung
    ;
    Linten, Dimitri
    ;
    Scholz, Mirko
    ;
    Huang, Yu-Ching
    ;
    Hellings, Geert
    CDM ESD events can be a potential threat to SoC designs or heterogeneous 3D ICs with multiple power domains. Inter-layer ( or interface) circuits may need a local CDM ESD clamp that can prevent the unexpected failure under CDM ESD stress. In this letter, two local CDM ESD clamp circuits are proposed. They show better clamping efficiency under 2-ns vfTLP stress.
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    Influence of InGaP and AlGaAs Schottky Layers on ESD Robustness in GaAs pHEMTs
    (2012-09-01)
    Chen, Shih-Hung
    ;
    Lin, Yueh-Chin
    ;
    Linten, Dimitri
    ;
    Scholz, Mirko
    ;
    Hellings, Geert
    GaAs high-electron-mobility transistors (HEMTs) have been widely used for radio-frequency (RF) applications due to the excellent material properties. One of the essential elements of the HEMTs is the gate Schottky barrier layer. InGaP has been proposed and proven as a better Schottky barrier material for the RF performance of the GaAs HEMTs. This letter investigates the influence of the GaAs HEMTs with two different Schottky layers, which are InGaP and AlGaAs on device transient characteristics under electrostatic discharge (ESD) stress. Although InGaP presents significant advantages on improving RF performance of GaAs HEMTs, it shows inferiority in ESD robustness.
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    Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection
    (2009-07-01)
    Chen, Shih-Hung
    ;
    Ker, Ming-Dou
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    MOS-triggered silicon-controlled rectifier (SCR) devices have been reported to achieve efficient on-chip electrostatic discharge (ESD) protection in deep-submicrometer CMOS technology. The channel length of the embedded MOS transistor in the MOS-triggered SCR device dominates the trigger mechanism and current distribution to govern the trigger voltage, holding voltage, on resistance, second breakdown current, and ESD robustness of the MOS-triggered SCR device. The embedded MOS transistor in the MOS-triggered SCR device should be optimized to achieve the most efficient ESD protection in advanced CMOS technology. In addition, the layout style of the embedded MOS transistor can be adjusted to improve the MOS-triggered SCR device for ESD protection.