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High Performance of Ge nMOSFETs Using SiO2 Interfacial Layer and TiLaO Gate Dielectric
(2010-01-01)
Chen, W. B.
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Chin, Albert
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Using a SiO2 interfacial layer and a high-kappa gate TiLaO dielectric, the TaN/TiLaO/SiO2 on Ge/Si nMOSFETs in this study showed a small 1.1-nm capacitance equivalent thickness, a good high field mobility of 201 cm(2)/(V . s) at 0.5 MV/cm, and a very low OFF-state leakage current of 3.5 x 10(-10) A/mu m. The self-aligned and gate-first metal-gate/high-kappa and Ge nMOSFETs were processed using standard ion implantation and 550 degrees C RTA. The proposed devices are fully compatible with current VLSI fabrication methods.