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Gate-First TaN/La2O3/SiO2/Ge n-MOSFETs Using Laser Annealing
(2010-11-01)
Chen, W. B.
;
Wu, C. H.
;
Shie, B. S.
;
Chin, Albert
;
電子工程學系及電子研究所
To improve device performance, laser annealing was applied to Ge n-MOSFETs, which gave a low sheet resistance of 68 Omega/sq, a small ideality factor of 1.3, and a large similar to 10(5) forward\reverse current in the source-drain n(+)/p junction. The laser-annealed gate-first TaN/La2O3/SiO2/Ge n-MOSFETs showed a high mobility of 603 cm(2)/Vs and a good mobility of 304 cm(2)/Vs at a 1.9-nm equivalent oxide thickness.
High-Performance Gate-First Epitaxial Ge n-MOSFETs on Si With LaAlO3 Gate Dielectrics
(2010-12-01)
Chen, W. B.
;
Cheng, C. H.
;
Chin, Albert
;
光電學院
;
電子工程學系及電子研究所
This brief presents high-performance Ge n-MOSFETs with good high-field mobility of 218 cm(2)/V . s at 0.5 MV/cm, low subthreshold swing (SS) of 108 mV/dec, small equivalent oxide thickness (EOT) of 1.6 nm, low 7 x 10(-10) A/mu m OFF-state leakage, small bias temperature instability of 31 mV at 1.2 V overdrive and 85 degrees C, and full process compatibility with current very large-scale integration fabrication. These are one of the best SS and high-field mobility data among gate-first Ge n-MOSFETs using epitaxial Ge on 6-in Si wafer and proper high-kappa LaAlO3 dielectric without using an interfacial layer. Using a different high-kappa HfAlO gate dielectric, the Ge n-MOSFETs showed poor leakage, large flatband voltage shift, and degraded EOT.
Flat band voltage control on low V-t metal-gate/high-kappa CMOSFETs with small EOT
(2009-07-01)
Chin, Albert
;
Chang, M. F.
;
Lin, S. H.
;
Chen, W. B.
;
Lee, P. T.
The unwanted high threshold voltage (V-t) is the major challenge for metal-gate/high-kappa CMOs especially at small equivalent-oxide-thickness (EOT). We have investigated the high V-t issue that is due to flat-band voltage (V-fb) roll-off at smaller EOT. A mechanism of charged oxygen vacancies formed by interface reaction was proposed to explain the V-fb roll-off effect. This interface reaction can be decreased by inserting a thin interfacial SiON and using novel low temperature process. The self-aligned and gate-first metal-gate/high-kappa CMCSFETs using these methods have achieved low V-t and good control of V-fb roll-off at small 0.6-1.2 nm EOT. Crown Copyright (C) 2009 Published by Elsevier B.V. All rights reserved,
High Performance of Ge nMOSFETs Using SiO2 Interfacial Layer and TiLaO Gate Dielectric
(2010-01-01)
Chen, W. B.
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Using a SiO2 interfacial layer and a high-kappa gate TiLaO dielectric, the TaN/TiLaO/SiO2 on Ge/Si nMOSFETs in this study showed a small 1.1-nm capacitance equivalent thickness, a good high field mobility of 201 cm(2)/(V . s) at 0.5 MV/cm, and a very low OFF-state leakage current of 3.5 x 10(-10) A/mu m. The self-aligned and gate-first metal-gate/high-kappa and Ge nMOSFETs were processed using standard ion implantation and 550 degrees C RTA. The proposed devices are fully compatible with current VLSI fabrication methods.
Gate-First TaN/La(2)O(3)/SiO(2)/Ge n-MOSFETs Using Laser Annealing
(2010-11-01)
Chen, W. B.
;
Wu, C. H.
;
Shie, B. S.
;
Chin, Albert
;
電子工程學系及電子研究所
To improve device performance, laser annealing was applied to Ge n-MOSFETs, which gave a low sheet resistance of 68 Omega/sq, a small ideality factor of 1.3, and a large similar to 10(5) forward everse current in the source-drain n(+)/p junction. The laser-annealed gate-first TaN/La(2)O(3)/SiO(2)/Ge n-MOSFETs showed a high mobility of 603 cm(2)/Vs and a good mobility of 304 cm(2)/Vs at a 1.9-nm equivalent oxide thickness.
Flat band voltage control on low V(t) metal-gate/high-kappa CMOSFETs with small EOT
(2009-07-01)
Chin, Albert
;
Chang, M. F.
;
Lin, S. H.
;
Chen, W. B.
;
Lee, P. T.
The unwanted high threshold voltage (V(t)) is the major challenge for metal-gate/high-kappa CMOs especially at small equivalent-oxide-thickness (EOT). We have investigated the high V(t) issue that is due to flat-band voltage (V(fb)) roll-off at smaller EOT. A mechanism of charged oxygen vacancies formed by interface reaction was proposed to explain the V(fb) roll-off effect. This interface reaction can be decreased by inserting a thin interfacial SiON and using novel low temperature process. The self-aligned and gate-first metal-gate/high-kappa CMCSFETs using these methods have achieved low V(t) and good control of V(fb) roll-off at small 0.6-1.2 nm EOT. Crown Copyright (C) 2009 Published by Elsevier B.V. All rights reserved,
Higher kappa Metal-Gate/High-kappa/Ge n-MOSFETs with < 1 nm EOT Using Laser Annealing
(2010)
Chen, W. B.
;
Shie, B. S.
;
Chin, Albert
;
Hsu, K. C.
;
Chi, C. C.
High performance metal-gate/high-kappa/Ge n-MOSFETs are reached with low 73 Omega/sq sheet resistance (R(s)), 1.10 ideality factor, 0.95 nm EOT, small 106 mV/dec sub-threshold slope (SS), good 285 cm(2)/Vs high-field (1 MV/cm) mobility and low 37 mV Delta V(t) PBTI (85 degrees C, 1 hr). This is achieved by using 30-ns laser annealing that leads to 57% higher gate capacitance, better n(+)/p junction and 10X better I(ON)/I(OFF).
High-Performance Gate-First Epitaxial Ge n-MOSFETs on Si With LaAlO(3) Gate Dielectrics
(2010-12-01)
Chen, W. B.
;
Cheng, C. H.
;
Chin, Albert
;
光電學院
;
電子工程學系及電子研究所
This brief presents high-performance Ge n-MOSFETs with good high-field mobility of 218 cm(2)/V . s at 0.5 MV/cm, low subthreshold swing (SS) of 108 mV/dec, small equivalent oxide thickness (EOT) of 1.6 nm, low 7 x 10(-10) A/mu m OFF-state leakage, small bias temperature instability of 31 mV at 1.2 V overdrive and 85 degrees C, and full process compatibility with current very large-scale integration fabrication. These are one of the best SS and high-field mobility data among gate-first Ge n-MOSFETs using epitaxial Ge on 6-in Si wafer and proper high-kappa LaAlO(3) dielectric without using an interfacial layer. Using a different high-kappa HfAlO gate dielectric, the Ge n-MOSFETs showed poor leakage, large flatband voltage shift, and degraded EOT.
High-field mobility metal-gate/high-kappa Ge n-MOSFETs with small equivalent-oxide-thickness
(2011-01-01)
Chen, W. B.
;
Cheng, C. H.
;
Lin, C. W.
;
Chen, P. C.
;
Chin, Albert
We fabricated high performance gate-last TaN/La(2)O(3)/SiO(2) on Ge n-MOSFET. Small equivalent-oxide-thickness (EOT) of 1.9-nm and high-field mobility of 258 cm(2)/V s at 0.75 MV/cm were obtained, which were attributed to the thin SiO(2)-like barrier layer and low process temperature to prevent interfacial reaction during post-deposition annealing (PDA). (C) 2010 Elsevier Ltd. All rights reserved.
Advanced Metal-Gate/High-kappa CMOS with Small EOT and Better High Field Mobility
(2012)
Chin, Albert
;
Chen, W. B.
;
Chen, P. C.
;
Wu, Y. H.
;
Chi, C. C.
Continuously down-scaling the operation voltage, saving energy, and maintaining high performance are the major challenge for CMOS device. Small 0.95 similar to 1.4 nm equivalent-oxide thickness (EOT) and 1.4 similar to 2.5X better mobility than universal SiO2/Si data are achieved in metal-gate/high-kappa/Ge CMOS at 1 MV/cm effective field (E-eff). These excellent performances were achieved by using interface engineering and novel process, to overcome the poor high-kappa/Ge interface reaction, low source-drain dopant activation, and n(+)/p ohmic contact. The all-Ge CMOS with measured higher electron and hole mobility has irreplaceable merits of much simpler process, lower cost, and potentially higher yield than the InGaAs-nMOS/Ge-pMOS platform for IC manufacture.

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