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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Chen, Wei-ZenSubject: search.filters.subject.PLL

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Now showing 1 - 3 of 3
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    A 3.12 pJ/bit, 19-27 Gbps Receiver with 2 Tap-DFE Embedded Clock and Data Recovery
    (2014)
    Hong, Zheng-Hao
    ;
    Chen, Wei-Zen
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A 19-27-Gb/s receiver comprising of a continuous time linear equalizer (CTLE) followed by a 2 tap decision feedback equalizer embedded clock and data recovery circuit is implemented. The hybrid CDR is operated at half rate, which is incorporated into a broad band PLL to facilitate ISI and jitter suppression over wide band operation. A quadrature relaxation type oscillator is proposed to provide the sampling phases without bulky inductors. Fabricated in a 40 nm CMOS technology, the whole receiver manifests a high energy efficiency of 3.12pJ/bit at 27 Gbps operation to compensate 20 dB channel loss at Nyquist frequency. The core area is 0.09 mm(2) only.
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    A Delta Sigma TDC with Sub-ps Resolution for PLL Built-in Phase Noise Measurement
    (2016)
    Chen, Wei-Zen
    ;
    Kuo, Po-I
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A sub-ps Delta Sigma TDC for PLL built-in phase noise measurement is proposed. Integrated with a 4.8 GHz PLL, the measured rms jitter integrated from 1kHz to 100 MHz by using spectrum analyzer E4448A and Delta Sigma TDC are 1.46 ps and 1.39 ps respectively, which manifests less than 5% discrepancy. The BIST circuit consumes 3mW from a 1.2V supply. Fabricated in TSMC 65nm CMOS process, the chip area is only 0.03mm(2).
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    A 160-GHz Frequency-Translation Phase-Locked Loop With RSSI Assisted Frequency Acquisition
    (2014-06-01)
    Chen, Wei-Zen
    ;
    Lu, Tai-You
    ;
    Wang, Yan-Ting
    ;
    Jian, Jhong-Ting
    ;
    Yang, Yi-Hung
    A 160-GHz frequency-translation PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3rd harmonic mixer incorporating a frequency tripler for frequency down conversion. A transformer-based VCO is utilized to alleviate capacitive and resistive load associated with varactor and succeeding buffer stages. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatic frequency sweeping and fast locking. Fabricated in 65 nm CMOS technology, the chip size is 0.92 mm(2). The PLL locking time is less than 3 mu s. This chip drains 24 mW from a 1.2 V power supply.