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Ultrathin N2O-oxide with atomically flat interfaces
(1997-05-01)
Chin, A
;
Chen, WJ
;
Lin, BC
;
Kao, JH
;
Tsai, C
Silicon oxide has been grown in a low pressure furnace using N2O. An atomically fiat SiO2 (N2O)/Si interface, as determined by high resolution transmission electron microscopy, has been achieved by desorbing the native oxide in situ for oxide thicknesses 11 to 38 Angstrom. The thickness variation of a 20 Angstrom N2O-oxide, grown on a 4 in. substrate <1 Angstrom. The excellent uniformity is attributed to the increased mean-free path of N2O molecules in the low pressure environment. Since only one Si plane was distorted beneath the N2O-oxide/Si interface, this suggests that thermal stress is not the limiting factor for obtaining an atomically smooth interface.
Thin oxides with in situ native oxide removal
(1997-09-01)
Chin, A
;
Chen, WJ
;
Chang, T
;
Kao, RH
;
Lin, BC
We have studied the inversion layer mobility of n-MOSFET's with thin-gate oxide of 20 to 70 Angstrom. Direct relationship of electron mobility to oxide/channel interface roughness was obtained from measured mobility of MOSFET's and high-resolution TEM. By using a low-pressure oxidation process with native oxide removed in situ prior to oxidation, atomically smooth interface of oxide/channel was observed by high-resolution TEM for oxide thicknesses of 11 and 38 Angstrom. The roughness increased to one to two monolayers of Si in a 55-Angstrom oxide. Significant mobility improvement was obtained from these oxides with smoother interface than that from conventional furnace oxidation. Mobility reduction with decreasing oxide thickness was observed in the 20- and 35-Angstrom oxide, with the same atomically smooth oxide/channel interface. This may be due to the remote Coulomb scattering from gate electrode or the gate field variation from poly-gate/oxide interface roughness.
Temperature-dependent transport properties of n(+) GaAs/low-temperature GaAs/n(+) GaAs structures grown by molecular beam epitaxy
(1996-06-01)
Chen, JF
;
Chen, NC
;
Chiu, SY
;
Wang, PY
;
Lee, WI
The temperature-dependent I-V characteristics of n(+) GaAs low-temperature GaAs(AlGaAs) n(+) GaAs structures in which the low-temperature layers were grown at 250, 350, and 450 degrees C were analyzed. Band conduction with an activation energy of 0.72 eV dominates at T>250 K. Hopping conduction dominates at T<250 K, where the resistivity was found to be insensitive to temperature. From this analysis, it is shown that Fermi level is pinned to an acceptorlike deep level of about 10(17) cm(-3), which lies at 0.72 eV below the conduction band. Measured capacitance can be described in terms of a parallel-plate capacitance with separation being equal to the expected growth thickness. Majority traps (electrons) were observed by deep-level transient spectroscopy with an activation energy about 0.72 eV, confirming the result of the resistivity analysis. In addition, the I-V characteristics were fitted to the simulated curves based on a simplified space-charge limited theory and the result was found to be consistent with the resistivity analysis. (C) 1996 American Institute of Physics.
High quality Al(Ga)As/GaAs/Al(Ga)As quantum wells grown on (111)A GaAs substrates
(1996-06-10)
Chin, A
;
Lee, K
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We report the growth of high quality molecular beam epitaxy (MBE) AlGaAs, AlGaAs/GaAs/ AlGaAs, and AlAs/GaAs/AlAs multiple quantum wells (MQWs) on (111)A GaAs substrates. For (111)A AlGaAs/GaAs/AlGaAs MQWs, there is no detectable photoluminescence (PL) at a growth temperature of 640 degrees C, and narrow PL linewidth can only be obtained at growth temperatures higher than 680 degrees C. A PL linewidth of 13.8 meV is measured at the growth temperature of 720 degrees C. To understand such growth temperature dependence of (111)A MQWs, we have investigated the material quality of (111)A AlGaAs at different growth temperatures. The strong PL integrated intensity of 640 degrees C grown (111)A AlGaAs indicates good material quality and a low concentration of non-radiative recombination centers. However, the broad PL linewidth of 640 degrees C grown (111)A AlGaAs indicates the strong compositional modulation and a rough growth front. We have used AlAs instead of AlGaAs in order to reduce the compositional modulation and smooth the interface. A PL linewidth of 13.4 meV is measured for 640 degrees C grown (111)A AlAs/GaAs/AlAs MQWs, which is the narrowest value for (111)A MQWs. (C) 1996 American Institute of Physics.
Improved electrical characteristics of CoSi2 using HF-vapor pretreatment
(1999-05-01)
Wu, YH
;
Chen, WJ
;
Chang, SL
;
Chin, A
;
Gwo, S
We have developed a simple process to form epitaxial CoSi2 for shallow junction. Prior to metal deposition, the patterned wafers were treated with HF-vapor passivation. As observed by scanning tunneling microscopy (STM), this HF, treatment drastically improves the native oxide-induced sur face roughness. The epitaxial behavior was confirmed by cross-sectional transmission electron microscopy (TEM), Decreased sheet resistance and leakage current, and improved thermal stability are displayed by the HF treated samples, which is consistent with STM and TEM results.
High quality epitaxial Si grown by a simple low pressure chemical vapor deposition at 550 degrees C
(1996-09-09)
Chin, A
;
Lin, BC
;
Chen, WJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We have designed a simple-hot wall low pressure chemical vapor deposition (LPCVD) system to grow high quality epitaxial Si films from 550 to 900 degrees C. The epitaxial film has been examined by scan electron microscopy for surface morphology, and by x-ray diffraction and cross-sectional transmission electron microscopy for crystallinity. Its quality has been found comparable to that of the substrate. Reduction of moisture and oxygen in the ambient is critical to the success of the growth at low temperatures. A combination of a leak-tight LPCVD reactor, a high flow rate Of 61/min of H-2 purge, and a pre-bake at high temperature of 950 degrees C has been used to achieve the reduction of moisture and oxygen. Degraded films form with increasing full width at half maximum of x-ray diffraction peak when a pre-bake at lower temperature is used. (C) 1996 American Institute of Physics.
Enhancement of the optical and electrical properties in InGaAlP/InGaP PIN heterostructures by rapid thermal annealing on misoriented substrate
(1996-07-01)
Chin, A
;
Lin, HY
;
Lin, BC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We have studied the optical and electrical properties of InGaAlP/InGaP PIN heterostructures by the effects of post-growth annealing, substrate misorientation and growth temperature. For the as-grown p-type In-0.5(Ga0.5Al0.5)(0.5)P, the 15 degrees misoriented sample shows the largest hole concentration of 1 x 10(18) cm(-3) as compared to 20 and 10 degrees misoriented samples. After annealing at 900 degrees C for 30 s, the hole concentration increases about three times to 2.6 x 10(18) cm(-3). The increased hole concentration is related to the four times enhanced photoluminescence (PL) intensity. In the In0.6Ga0.4P/In-0.5(Ga0.6Al0.4)(0.5)P stained multiple quantum wells, the post-growth annealing also improves the PL integrated intensity. The PL intensity on an as-grown sample decreases with the increased degree of misorientation, while the PL peak energy increases with the increased degree of misorientation, from 0 degrees, 2 degrees, 10 degrees toward 15 degrees. The PL intensities are larger for samples grown at 760 degrees C than those grown at 700 degrees C. Copyright (C) 1996 Elsevier Science Ltd.
Microstructure and subpicosecond photoresponse in GaAs grown by molecular beam epitaxy at very low temperatures
(1996-07-15)
Chin, A
;
Chen, WJ
;
Ganikhanov, F
;
Lin, GR
;
Shieh, JM
Cross-sectional transmission electron microscopy (TEM) and femtosecond (fs) reflectivity are used to study (Ga,As) compound grown at low temperatures from 160 to 70 degrees C, A columnar polycrystalline GaAs is observed for samples grown at 160 degrees C while it appears amorphous for samples grown at temperatures below 120 degrees C, The successful growth of amorphous (Ga,As) at 70 degrees C, instead of a mixture of metallic Ga droplets and As solids, suggests that the decomposition of As-4 molecules may be catalyzed by the surface Ga. Upon annealing, all samples become polycrystalline before epitaxial solid state regrowth eventually dominates and the whole sample becomes single crystal for long enough annealing. Carrier lifetime of 230 fs is measured for the as-grown amorphous sample. For the annealed sample, the photoresponse exhibits a fast initial decay of 120 fs and a much slower secondary decay of 33 ps. The initial decay is attributed to the formation of fine polycrystalline grains (similar to 500 Angstrom in size) whose grain boundaries provide effective carrier traps and recombination centers. (C) 1996 American Institute of Physics.
Electrical and structural characteristics of PbTiO3 thin films with ultra-thin Al2O3 buffer layers
(2002-02-17)
Sun, CL
;
Chen, SY
;
Yang, MY
;
Chin, A
;
材料科學與工程學系
Polycrystalline PbTiO3 thin films have been prepared on Si substrates with ultra-thin SiO2 and Al2O3 buffer layers by chemical solution deposition, respectively. Although capacitance-voltage characteristics show hysteresis loops in both cases, the memory window of PbTiO3/Al2O3 stacked dielectric is 3.3V larger than that on SiO2. In addition, well-behaved capacitance-voltage characteristics are only obtained in PbTiO3/Al(2)o(3) and the PbTiO3 films on Al2O3 have the dielectric constant of 116 larger than 42 of PbTiO3 films on SiO2. The leakage current density of PbTiO3/Al2O3 dielectric is 1.3 x 10(-7) A cm(-2) at -2.5 V, which is low enough for deep sub-mum application. (C) 2002 Elsevier Science B.V. All rights reserved.
The effect of native oxide on thin gate oxide integrity
(1998-11-01)
Chin, A
;
Lin, BC
;
Chen, WJ
;
Lin, YB
;
Thai, C
We have studied the effect of native oxide on thin gate oxide integrity. Much improved leakage current of gate oxide can be obtained by in situ desorbing the native oxide using a HF-vapor treated and H-2 backed process. Furthermore, extremely sharp interface between oxide and Si is obtained, and good oxide reliability is achieved even under a high current density stress of 11 A/cm(2) and a large charge injection of 7.0 x 10(4) C/cm(2). The presence of native oxide will increase the interface roughness, gate oxide leakage current and stress-induced hole trap.

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