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Gate-First TaN/La2O3/SiO2/Ge n-MOSFETs Using Laser Annealing
(2010-11-01)
Chen, W. B.
;
Wu, C. H.
;
Shie, B. S.
;
Chin, Albert
;
電子工程學系及電子研究所
To improve device performance, laser annealing was applied to Ge n-MOSFETs, which gave a low sheet resistance of 68 Omega/sq, a small ideality factor of 1.3, and a large similar to 10(5) forward\reverse current in the source-drain n(+)/p junction. The laser-annealed gate-first TaN/La2O3/SiO2/Ge n-MOSFETs showed a high mobility of 603 cm(2)/Vs and a good mobility of 304 cm(2)/Vs at a 1.9-nm equivalent oxide thickness.
High-Performance Gate-First Epitaxial Ge n-MOSFETs on Si With LaAlO3 Gate Dielectrics
(2010-12-01)
Chen, W. B.
;
Cheng, C. H.
;
Chin, Albert
;
光電學院
;
電子工程學系及電子研究所
This brief presents high-performance Ge n-MOSFETs with good high-field mobility of 218 cm(2)/V . s at 0.5 MV/cm, low subthreshold swing (SS) of 108 mV/dec, small equivalent oxide thickness (EOT) of 1.6 nm, low 7 x 10(-10) A/mu m OFF-state leakage, small bias temperature instability of 31 mV at 1.2 V overdrive and 85 degrees C, and full process compatibility with current very large-scale integration fabrication. These are one of the best SS and high-field mobility data among gate-first Ge n-MOSFETs using epitaxial Ge on 6-in Si wafer and proper high-kappa LaAlO3 dielectric without using an interfacial layer. Using a different high-kappa HfAlO gate dielectric, the Ge n-MOSFETs showed poor leakage, large flatband voltage shift, and degraded EOT.
High Performance of Ge nMOSFETs Using SiO2 Interfacial Layer and TiLaO Gate Dielectric
(2010-01-01)
Chen, W. B.
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Using a SiO2 interfacial layer and a high-kappa gate TiLaO dielectric, the TaN/TiLaO/SiO2 on Ge/Si nMOSFETs in this study showed a small 1.1-nm capacitance equivalent thickness, a good high field mobility of 201 cm(2)/(V . s) at 0.5 MV/cm, and a very low OFF-state leakage current of 3.5 x 10(-10) A/mu m. The self-aligned and gate-first metal-gate/high-kappa and Ge nMOSFETs were processed using standard ion implantation and 550 degrees C RTA. The proposed devices are fully compatible with current VLSI fabrication methods.
High-Performance Charge-Trapping Flash Memory Device With an Ultrathin 2.5-nm Equivalent-Si3N4-Thickness Trapping Layer
(2012-01-01)
Tsai, C. Y.
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We made the MoN-[SiO2-LaAlO3]-[Ge-HfON]-[LaAlO3-SiO2]-Si charge-trapping (CT) Flash device with a record-thinnest 2.5-nm equivalent-Si3N4-thickness trapping layer, a large 4.4-V initial memory window, a 3.2-V ten-year extrapolated retention window at 125 degrees C, and a 3.6-V endurance window at 106 cycles, under very fast 100 mu s and low +/- 16-V program/erase pulses. These were achieved using Ge reaction with a HfON trapping layer for better CT and retention.
Ultra-Low Power Green Electronic Devices
(2015)
Yi, S. H.
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Power consumption is the crucial challenge for electronics. To lower the DC leakage power (P-DC), we applied the high-kappa gate dielectric to CMOS from the physics of Q equivalent to CV. More than 2 orders of magnitude lower P-DC is obtained at small 0.5 similar to 0.9 nm equivalent-oxide-thickness (EOT). The high-kappa dielectric also increases the charge controllability of flash memory and decrease the V-T disturbance by nearly cells, which improves cell density and cost. The AC power (P-AC) can be lowered by using high-mobility Ge CMOS at a lower V-D and 3D IC with a small capacitance, from basic physics of P-AC equivalent to CV(D)(2)f/2.
High-field mobility metal-gate/high-kappa Ge n-MOSFETs with small equivalent-oxide-thickness
(2011-01-01)
Chen, W. B.
;
Cheng, C. H.
;
Lin, C. W.
;
Chen, P. C.
;
Chin, Albert
We fabricated high performance gate-last TaN/La(2)O(3)/SiO(2) on Ge n-MOSFET. Small equivalent-oxide-thickness (EOT) of 1.9-nm and high-field mobility of 258 cm(2)/V s at 0.75 MV/cm were obtained, which were attributed to the thin SiO(2)-like barrier layer and low process temperature to prevent interfacial reaction during post-deposition annealing (PDA). (C) 2010 Elsevier Ltd. All rights reserved.
Metal-Gate/High-kappa/Ge nMOS at Small CET With Higher Mobility Than SiO2/Si at Wide Range Carrier Densities
(2013-02-01)
Liao, C. C.
;
Ku, T. C.
;
Lin, M. H.
;
Zeng, Lang
;
Kang, Jinfeng
High-performance TaN/TiLaO/La2O3/SiO2/(111)-Ge nMOSFETs show high mobility of 432 cm(2)/V . s at 10(13) cm(-2) carrier density (N-s), good 1.05 junction ideality factor, and small subthreshold swing of 101 mV/dec, at a small 1.1-nm capacitance-equivalent thickness (CET). This is the first report of higher mobility in the Ge nMOSFET than SiO2/Si universal mobility at wide medium-high N-s range and small CET of 1.1 nm, which is attributed to using the (111)-Ge substrate, 30-ns laser annealing, SiO2 interfacial layer, and YbGex/n-Ge contact.
Higher Gate Capacitance Ge n-MOSFETs Using Laser Annealing
(2011-04-01)
Chen, W. B.
;
Shie, B. S.
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
By applying laser annealing (LA) on both gate dielectrics and source/drain activation, the TaN/ZrO(2)/La(2)O(3)/SiO(2) on Ge n-MOSFETs shows a high gate capacitance density, a small n(+)/p-junction ideality factor of 1.10, a small subthreshold swing (SS) of 106 mV/dec, and a good high-field mobility of 285 or 340 cm(2)/V . s after gate leakage correction at 1 MV/cm, at a small 0.95-nm equivalent oxide thickness (EOT). To the best of our knowledge, this is the first demonstration of significantly high gate capacitance in MOSFETs by LA. This is also the highest 1-MV/cm mobility at the smallest EOT of Ge n-MOSFETs and better than the SiO(2)/Si universal mobility.

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