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A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist
(2014-12-01)
Lien, Nan-Chun
;
Chu, Li-Wei
;
Chen, Chien-Hen
;
Yang, Hao-I.
;
Tu, Ming-Hsien
This paper presents a cross-point 512 kb 8 T pipeline static random-access memory (SRAM). The cross-point structure eliminates write half-select disturb to facilitate bit-interleaving architecture for enhanced soft error immunity. The design employs boosted word-line (WL) for improving both read performance and write-ability. A ripple bit-line (RiBL) structure provides 30%-44% read access performance improvement and 2x-3.5x variation immunity at 0.7 V compared with the conventional hierarchical bit-line (HiBL) schemes. An adaptive data-aware write-assist (ADAWA) with VCS tracking is employed to further enhance the write-ability while ensuring adequate stability for half-selected cells on the selected bit-lines. An adaptive voltage detector (AVD) with binary boosting control is used to mitigating gate electric over-stress. The design is implemented in UMC 40 nm low-power (40LP) CMOS technology. The 512 kb test chip operates from 1.5 V to 0.65 V, with maximum operation frequency of 800 MHz@1.1 V and 200 MHz@0.65 V. The measured power consumption is 0.5 mW/MHz (active) and 4.4 mW (standby) at 1.1 V, and 0.107 mW/MHz (active) and 0.367 mW (standby) at 0.65 V.
Self-Matched ESD Cell in CMOS Technology for 60-GHz Broadband RF Applications
(2010)
Lin, Chun-Yu
;
Chu, Li-Wei
;
Ker, Ming-Dou
;
Lu, Tse-Hua
;
Hung, Ping-Fang
A self-matched ESD cell library has been implemented in a commercial sub-100nm CMOS process for 60-GHz broadband RF applications. This ESD cell library has reached the 50-Omega input/output matching to reduce the design complexity for RF circuit designer and to provide suitable electrostatic discharge (ESD) protection. Experimental results of this ESD cell library have successfully verified the ESD robustness and the RF characteristics in the 60-GHz frequency band. This self-matched ESD cell library is easily to be used for ESD protection design in the 60-GHz broadband RF applications.
Controlled growth of the silicide nanostructures on Si bicrystal nanotemplate at a precision of a few nanometres
(2011)
Hsin, Cheng-Lun
;
Wu, Wen-Wei
;
Chu, Li-Wei
;
Hsu, Hung-Chang
;
Chen, Lih-Juann
A nanotemplate of Si bicrystal was fabricated by wafer bonding. The surface electronic energy arrangement on the surface of the Si bicrystal has been measured by scanning tunneling microscopy. The stress effect on the stepped growth of titanium silicide nanorods on Si bicrystal was observed in an ultrahigh vacuum transmission electron microscope in real time. The growth behavior of the nanorods was found to be affected by the underlying dislocation arrays significantly. For a dislocation interspacing of 3.1 nm, the dislocation arrays confined the shape of the nanoclusters and nanorods. Compared to the time of the nanorod remaining at the same length, the elongating time is more than two orders of magnitude shorter. The stepped growth behavior is attributed to the stress contour of the surface strain induced by the underlying dislocation network. This study is constructive to the basic understanding of the stress effect on the initial stage of the reaction of metals on Si and the observation may be applied to nanostructure growth for future applications and design.
Design of Analog Pixel Memory for Low Power Application in TFT-LCDs
(2011-02-01)
Chu, Li-Wei
;
Liu, Po-Tsun
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
光電工程學系
Two types of analog memory cells realized in a 3-m low temperature polycrystalline silicon (LTPS) technology are proposed to achieve low power application for thin film transistor liquid crystal displays (TFT-LCDs). By employing the inversion signal in the storage capacitor with complementary source follower, the frame rate to refresh the static image can be reduced from 60 to 3.16 Hz with the output decay less than 0.1 V under the input data from 1 to 4 V. To further diminish threshold voltage drop from source follower structure, a compensation technique is implemented to the proposed analog memory cells. In addition, asymmetric output voltage can be also minimized by adding a reference voltage to achieve symmetric output waveform.
Robust ESD Protection Design for 40-Gb/s Transceiver in 65-nm CMOS Process
(2013-11-01)
Lin, Chun-Yu
;
Chu, Li-Wei
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
To protect a 40-Gb/s transceiver from electrostatic discharge (ESD) damages, a robust ESD protection design has been proposed and realized in a 65-nm CMOS process. In this paper, diodes are used for ESD protection and inductors are used for high-speed performance fine tuning. Experimental results of the test circuits have been successfully verified, including highspeed performances and ESD robustness. The proposed design has been further applied to a 40-Gb/s current-mode logic (CML) buffer. Verified in silicon chip, the 40-Gb/s CML buffer with the proposed design can achieve good high-speed performance and high ESD robustness.
Design of Dual-Band ESD Protection for 24-/60-GHz Millimeter-Wave Circuits
(2013-03-01)
Chu, Li-Wei
;
Lin, Chun-Yu
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
光電工程學系
To effectively protect the millimeter-wave (MMW) circuits in nanoscale CMOS technology from electrostatic discharge (ESD) damages, a dual-band ESD protection cell for 24-/60-GHz ESD protection is presented in this paper. The proposed ESD protection cell consisted of a diode, a silicon-controlled rectifier, a PMOS, and two inductors. To verify the dual-band characteristics and ESD robustness, the proposed ESD protection circuit had been applied to a 24-/60-GHz low-noise amplifier (LNA). The measurement results showed over-2-kV human-body-model ESD robustness with little performance degradation on LNA. The proposed dual-band ESD protection cell was suitable for circuit designers for them to easily apply ESD protection in the dual-band MMW circuits.
Design of Bidirectional and Low Power Consumption Gate Driver in Amorphous Silicon Technology for TFT-LCD Application
(2013-02-01)
Zheng, Guang-Ting
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Liu, Po-Tsun
;
Wu, Meng-Chyi
;
Chu, Li-Wei
;
Yang, Meng-Chuan
A new gate driver has been designed and fabricated by amorphous silicon (a-Si) technology. With utilizing four clock signals in the design of gate driver on array (GOA), the pull-up transistor has ability for both output charging and discharging, and layout size of the proposed gate driver can be narrowed for bezel panel application. Moreover, lower duty cycle of clock signals can decrease static power loss to further reduce the overall power consumption of the proposed gate driver. The scan direction of the proposed gate driver can be adjusted by switching two direct control signals to present the reversal display of image. The proposed gate driver has been successfully demonstrated in a 4.5-inch WVGA (480 x RGB x 800) TFT-LCD panel and passed reliability tests of the supporting foundry.
Large-Swing-Tolerant ESD Protection Circuit for Gigahertz Power Amplifier in a 65-nm CMOS Process
(2013-02-01)
Lin, Chun-Yu
;
Tsai, Shiang-Yu
;
Chu, Li-Wei
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
The signal swing at output pad of some radio-frequency (RF) power amplifiers (PAs) may be higher than the supply voltage. To protect the gigahertz large-swing power amplifier from electrostatic discharge (ESD) damage in nanoscale CMOS process, a large-swing-tolerant ESD protection circuit is presented in this paper. The proposed ESD protection circuit had been designed, fabricated, and characterized in a 65-nm CMOS process, where it can achieve low parasitic capacitance, large swing tolerance, high ESD robustness, and good latchup immunity. The proposed ESD protection circuit had been further applied to a 2.4-GHz PA to provide 3-kV human-body-model (HBM) ESD robustness without degrading the RF performances.
Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process
(2011-08-01)
Lin, Chun-Yu
;
Chu, Li-Wei
;
Ker, Ming-Dou
;
交大名義發表
;
National Chiao Tung University
The configurable electrostatic discharge (ESD) protection cells have been implemented in a commercial 65-nm CMOS process for 60-GHz RF applications. The distributed ESD protection scheme was modified to be used in this work. With the consideration of parasitic capacitance from I/O pad, the ESD protection cells have reached the 50-Omega input/output matching to reduce the design complexity for RF circuit designer and to provide suitable ESD protection. Experimental results of these ESD protection cells have successfully verified the ESD robustness and the RF characteristics in the 60-GHz frequency band. These ESD protection cells can easily be used for ESD protection design in the 60-GHz RF applications, and accelerate the design cycle. (C) 2011 Elsevier Ltd. All rights reserved.
Orientation-Dependent Room-Temperature Ferromagnetism of FeSi Nanowires and Applications in Nonvolatile Memory Devices
(2011-08-11)
Hung, Shih-Wei
;
Wang, Terry Tai-Jui
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Chu, Li-Wei
;
Chen, Lih-Juann
;
材料科學與工程學系
Self-catalyzed growth of FeSi nanowires has been achieved via a spontaneous chemical reaction method. The room-temperature ferromagnetism behavior compared to that of bulk FeSi at 4 K is attributed to the enhancement of magnetic coupling behavior correlated to different crystalline orientations. The resistivity of the single-stem FeSi nanowire was determined to be 2650 mu Omega.cm. The fabricated memory devices based on FeSi nanowires showed significant C-V hysteresis, exhibiting the memory effect. The strong memory effect can be accounted for by the presence of defects or dangling bonds on the surface of the FeSi nanowires embedded in the SiO(2) layer, which enhances the trapping density for nonvolatile memory applications.

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