學術出版;;Publications

Permanent URI for this communityhdl:11536/1

收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

Browse

🏛️國立陽明交通大學機構典藏

Search Results

Now showing 1 - 10 of 12

Exploration and Evaluation of Low-Dropout Linear Voltage Regulator with FinFET, TFET and Hybrid TFET-FinFET Implementations.
(2017-01-01)
Chang, Chia-Ning
;
Chen, Yin-Nien
;
Huang, Po-Tsang
;
Su, Pin
;
Chuang, Ching-Te
This paper investigates and evaluates analog and digital low-dropout linear voltage regulators (LDO) with FinFET, TFET and hybrid TFET-FinFET implementations. We utilize Sentaurus physics-based atomistic 3D TCAD mixed-mode simulations for device characteristics and HSPICE with look-up tables based on Verilog-A models calibrated with TCAD simulation results. Frequency response, load regulation and power supply rejection ratio (PSRR) are evaluated for analog LDOs under low, medium and high bias-current conditions. The results indicate that for analog implementations, TFET-LDO and hybrid-LDO provide better loop-gain and PSRR than FinFET-LDO under low and medium operating currents, whereas at higher operating current, FinFET implementation would outperform. As operating voltage is reduced, the performances of analog implementations degrade, and digital implementations become favorable for VIN below around 0.55V. We further show that for digital LDO, all FinFET implementation provides superior performance over all TFET and hybrid TFET-FinFET implementations.
Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits
(2012-08-01)
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Chen, Yin-Nien
;
Su, Pin
;
Chuang, Ching-Te
This paper analyzes the impacts of single-charged-trap-induced random telegraph noise (RTN) on FinFET devices in tied- and independent-gate modes, 6T static random access memory (SRAM) cell stability, and several basic logic circuits. The dependence of RTN on trap location, EOT, and temperature is evaluated through 3-D atomistic TCAD simulation. It is observed that the charged trap located near the bottom of sidewall (gate) interface and in the middle region between the source and drain will result in the most significant impact. EOT scaling and higher operating temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependence on the location of the trap and bias-dependent current-conduction path are analyzed. We show that the planar BULK device, with larger subthreshold swing (S.S.) and comparable trap-induced V-T shift, exhibits less nominal RTN degradation than FinFET for traps placed in the worst position. However, the larger variability and surface conduction characteristic of the planar BULK device lead to broader dispersion and larger worst case RTN degradation than the FinFET device with smaller variability and volume conduction. For traps randomly placed across the interface, similar RTN amplitude dispersions are observed for FinFET and planar BULK devices except in the vicinity of distribution tail due to the strong interaction between the charged trap and discrete random dopants in planar BULK devices. For 6T FinFET SRAM cell, the READ static noise margin of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage (V-dd), the importance of RTN on subthreshold cell stability increases. Moreover, the leakage and delay of FinFET inverters, two-way NAND, and two-to-one multiplexer are investigated using 3-D TCAD mixed-mode simulations. The RTN is found to cause similar to 24%-27% and similar to 13%-15% variations in leakage and delay at V-dd = 0.4 V, respectively, for the logic circuits evaluated.
Evaluation of Energy-Efficient Latch Circuits with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications
(2015)
Wu, Tse-Ching
;
Chen, Chien-Ju
;
Chen, Yin-Nien
;
Hu, Vita Pi-Ho
;
Su, Pin
In this paper, we investigate the hybrid TFET-FinFET latch circuits and compare the clock-to-Q delay, dynamic energy, leakage power and energy-delay product (EDP) with all FinFET and all TFET implementations in near-threshold region. We use atomistic 3D TCAD mixed-mode simulations for transistor characteristics and HSPICE circuit simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. Four types of latch circuits are evaluated, including standard clocked CMOS latch (SCCL), low-voltage (CMOS)-M-2 latch (LVCL), master-slave transmission-gate latch pair (MTLP) and pulse-triggered latch (PTL). In the hybrid design, TFETs are used for critical path to reduce the clock-to-Q delay, and FinFETs are used for the rest of the circuits to reduce the power consumption. The hybrid latch circuits are shown to offer comparable or better clock-to-Q delays while exhibiting superior EDP compared with all TFET implementations. Among the four types of latch circuits, the hybrid TFET-FinFET LVCL exhibits the most significant clock-to-Q delay and EDP improvements at low operating voltage (< 0.30V). With work function variation (WFV) and fin line-edge roughness (LER), the hybrid LVCL exhibits superior and comparable EDP variability compared with all FinFET and all TFET implementations at 0.25V.
Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFET
(2013-10-01)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
We present a comparative leakage analysis of germanium-on-insulator (GeOI) FinFET and germanium on bulk substrate FinFET (Ge bulk FinFET) at device and circuit levels. Band-to-band tunneling (BTBT) leakage-induced bipolar effect is found to result in an amplified BTBT leakage for GeOI FinFET. Device and circuit designs to mitigate the amplified BTBT leakage of GeOI FinFETs are suggested. The effectiveness of various high threshold voltage technology options including increasing channel doping, increasing gate length and drain-side underlap for leakage reduction is analyzed.
Investigation of Single-Trap-Induced Random Telegraph Noise for Tunnel FET Based Devices, 8T SRAM Cell, and Sense Amplifiers
(2013)
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Chen, Yin-Nien
;
Su, Pin
;
Chuang, Ching-Te
This paper analyzes the impacts of Random Telegraph Noise (RTN) caused by a single acceptor-type trap on Tunnel FET (TFET) based devices, 8T SRAM cell and sense amplifiers. 3D atomistic TCAD simulations accounting for the impact of localized/negatively-charged trap are utilized to assess the dependence of RTN amplitude (Delta I-D/I-D) on trap location and device geometry. Our results indicate that significant RTN impact occurs for trap located near the tunneling junction. The device design strategies (thinner EOT, W-fin and longer L-eff) to improve TFET device characteristics are found to increase the susceptibility to RTN. Furthermore, TFET-based standard 8T SRAM cell and several commonly used sense amplifiers including Current Latch Sense Amplifier (CLSA), Voltage Latch Sense Amplifier (VLSA), and single-ended large-signal inverter sense amplifier are examined using atomistic 3D TCAD mixed-mode simulations. The presence of RTN is shown to cause extra similar to 16% variations in cell stability (at V-dd = 0.3V) and additional similar to 80mV variation in offset voltage for sense amplifiers at V-dd = 0.5V.
Device Design and Analysis of Logic Circuits and SRAMs for Germanium FinFETs on SOI and Bulk Substrates
(2013)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
A comparative analysis of Germanium-on-Insulator FinFET (GeOl FinFET) and Germanium on bulk substrate FinFET (Ge bulk FinFET) at device and circuit level with respect to Si counterparts is presented. GeOI FinFET shows larger leakage current than Ge bulk FinFET due to the parasitic bipolar effect triggered by the band-to-band tunneling (BTBT) leakage. The effectiveness of different dual-Vt technology options including increasing channel doping, increasing gate length and drain-side underlap for leakage reduction is analyzed for GeOl and Ge bulk FinFET circuits and SRAMs. An optimum asymmetrie underlap design in SRAM using asymmetrie underlap pull-up and access transistors (PUAX-asym) is proposed. GeOl and Ge bulk FinFETs with asymmetrie underlap design show significant improvement in leakage-delay performance and stability in logic circuits and SRAM cells.
Variation Tolerant CLSAs for Nanoscale Bulk-CMOS and FinFET SRAM
(2012)
Tsai, Ming-Fu
;
Tsai, Jen-Huan
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
In this paper, we propose three Current-Latch-based Sense Amplifiers (CLSA) configurations for nanoscale Bulk-CMOS SRAM and several CLSAs using FinFET devices with independently-controlled-gate. Extensive simulations suggest the proposed structures are robust against random offset errors. The proposed CLSA structures feature significant offset suppression capabilities with sigma(offset) reduction up to 74% (76%) in 40nm Bulk-CMOS (25nm FinFET-SOI) technology compared with the conventional CLSA. Meanwhile, up to 27% (52%) shorter sensing delay, 71% (77%) shorter Time-To-Sense and 73% (76%) lower bit-line power consumption are achieved in 40nm Bulk-CMOS (25nm FinFET-SOI). Finally, the proposed CLSA structures significantly enhance the sensing yield and affordable number of cells per bit-line, thus improving the array efficiency hence overall area and performance/power as well.
A Comprehensive Comparative Analysis of FinFET and Trigate Device, SRAM and Logic Circuits
(2012)
Pao, Chia-Hao
;
Fan, Ming-Long
;
Tsai, Ming-Fu
;
Chen, Yin-Nien
;
Hu, Vita Pi-Ho
We present a comprehensive comparative analysis of FinFET and Trigate device characteristics, 6T SRAM stability and logic circuits. The impact of intrinsic random device variations, including fin Line Edge Roughness (LER), Work Function Variation (WFV) and fin width scaling on FinFET and Trigate device Subthreshold Slope (S. S.), V-T, 6T SRAM Read Static Noise Margin (RSNM) and Write Static Noise Margin (WSNM) are investigated and compared by using 3D atomistic TCAD simulation. The results indicate that Trigate device shows slightly better variability control under the same electrical width and fin width (10nm and 7nm) considering fin LER and WFV. Next, we investigate the impact of single charged trap induced Random Telegraph Noise (RTN) on FinFET and Trigate device characteristics, 6T SRAM and logic circuits. The top-gate and the lower fin height of Trigate device under the same electrical width and fin width cause the current density to concentrate close to the bottom of the fin, resulting in stronger dependence on the location of the trap, larger RTN Delta I-D/I-D amplitude and larger Delta V-T with a trap placed at the worst position under fin LER and WFV. The impact of RTN trapping/detrapping on 6T SRAM RSNM, the leakage-delay of inverter, Two-Way NAND and 2-To-1 Multiplexer (MUX) are examined. With degreasing supply voltage, the RTN degradation of Trigate SRAM RSNM and logic circuits become larger compared with the FinFET counterparts.
Impacts of Random Telegraph Noise on FinFET Devices, 6T SRAM cell, and Logic Circuits
(2012)
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Chen, Yin-Nien
;
Su, Pin
;
Chuang, Ching-Te
This paper analyzes the impacts of single trap induced Random Telegraph Noise (RTN) on scaled FiriFET devices in tied-gate and independent-gate modes, 6T SRAM cell and logic circuits. The dependence of RTN amplitude on trap location, EOT and temperature is evaluated through 3D atomistic TCAD simulations. It is observed that charged trap located near the bottom of sidewall (gate) interface, in the middle region between the source/drain results in most significant impact. EOT scaling and higher temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependency on the location of the trap and current conduction path are analyzed. We show that planar BULK device, with larger Subthreshold Swing (S.S.) and comparable trap-induced V-T shift (Delta V-T), exhibits less nominal RTN degradation than FinFET for trap placed in the worst position. However, the larger variability and surface conduction characteristic of planar BULK device result in broader dispersion and larger worst-case degradation than FinFET with smaller variability and volume conduction inside the silicon fin. For FiriFET 6T SRAM cell, the READ Static Noise Margin (RSNM) of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage (V-dd), the relative importance of RTN on the cell stability increases. The leakage/delay of FinFET inverter, 2-Way NAND and 2-To-1 multiplexer are investigated using mixed-mode TCAD simulations. The existence of RTN is found to cause similar to 24-27% and 13-15% variation in leakage and delay at V-dd=0.4V, respectively, for the logic circuits evaluated.
Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs
(2012-07-01)
Hsieh, Chien-Yu
;
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Su, Pin
;
Chuang, Ching-Te
In this work, we propose three novel independently-controlled-gate Schmitt Trigger (IG_ST) FinFET SRAM cells for sub-threshold operation. The proposed IG_ST 8 T SRAM cells utilize split-gate FinFET devices with the front-gate devices serving as the stacking devices, and the back-gate devices serving as the intermediate node conditioning devices to provide built-in feedback mechanism for Schmitt Trigger action, thus reducing the cell transistor count/area and achieving improved static noise margin (SNM) and better tolerance to process variation and random variations. 3-D mixed-mode simulations are used to evaluate the Read static noise margin (RSNM), Write static noise margin (WSNM), hold static noise margin (HSNM), and Standby leakage of proposed cells, and results are compared with the standard 6 T cells and previously reported 10 T Schmitt Trigger sub-threshold SRAM cells. Compared with the conventional tied-gate 6 T cell, the proposed IG_ST SRAM cells demonstrate 1.81X and 2.11X higher nominal RSNM at V-CS = 0.4 and 0.15 V, respectively. The cell layouts and areas are assessed based on scaled ground rules from 32 nm node, and the density advantage over previously reported 10 T Schmitt Trigger sub-threshold SRAM cells are illustrated. The cell AC performance (Read access time, Write time, and Read access time versus the number of cells per bit-line considering worst-case data pattern for bit-line leakage) and temperature dependence are evaluated, and shown to be adequate for the intended sub-threshold applications. Compared with previously reported 10 T Schmitt Trigger sub-threshold SRAM cells, the proposed cells exhibit comparable or better RSNM, higher density, and lower Standby leakage current. 3-D mixed-mode Monte Carlo simulations are performed to investigate the impacts of process variations (L-eff, EOT, W-fin, and H-fin) and random variations (Gate LER and Fin LER) on RSNM, WSNM, and HSNM. Our results indicate that even at the worst corner, two of the proposed cells can provide sufficient margin of mu/sigma ratio.

學術出版;;Publications

Browse

Filters

Settings

Sort By

Results per page

🏛️國立陽明交通大學機構典藏

Search Results