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Evaluation of Monolithic 3-D Logic Circuits and 6T SRAMs With InGaAs-n/Ge-p Ultra-Thin-Body MOSFETs
(2016-03-01)
Yu, Kuan-Chin
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
This paper evaluates monolithic 3-D logic circuits and 6T SRAMs composed of InGaAs-n/Ge-p ultra-thin-body MOSFETs while considering interlayer coupling through TCAD mixed-mode model. This paper indicates that monolithic 3-D InGaAs/Ge logic circuits provide equal leakage and better delay performance compared with planar 2-D structure through optimized 3-D layout. The monolithic 3-D InGaAs/Ge 6T SRAMs can simultaneously improve the cell stability and performance through optimized 3-D layout. We suggest two 3-D SRAM layout designs for high performance and low power applications, respectively. Moreover, with optimized 3-D layout designs, InGaAs/Ge logic circuits exhibit larger delay improvement, and the 6T SRAMs exhibit larger read access time and time-to-write improvement compared with Si counterparts.
Impacts of NBTI and PBTI on Ultra-Thin-Body GeOI 6T SRAM Cells
(2015)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
This paper investigates the impacts of Negative and Positive Bias Temperature Instabilities (NBTI and PBTI) on the stability and performance of Ultra-Thin-Body (UTB) GeOI 6T SRAM cells compared with the SOI counterparts. Worst case stress scenarios for Read and Write operations are analyzed. For UTB GeOI SRAM cells, PBTI dominates the degradations in RSNM, HSNM, cell Read access time, and Time-to-Write, while for UTB SOI SRAM cells, NBTI dominates the degradations in RSNM, HSNM, and Time-to-Write. WSNM only slightly degrades due to NBTI/PBTI. Threshold voltage design and Word-Line Under-Drive (WLUD) Read-Assist techniques are analyzed to compensate the stability degradation due to NBTI/PBTI for UTB GeOI SRAM cells. Compared with the nominal UTB GeOI SRAM cells with low Vth design, UTB GeOI SRAM cells with high Vth design suffer less NBTI/PBTI degradations and exhibit significant improvement in RSNM and HSNM, and comparable performance compared with the nominal UTB SOI SRAM cells.
Evaluation of Read-and Write-Assist Circuits for GeOI FinFET 6T SRAM Cells
(2014-01-01)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
;
電機工程學系
This paper evaluates the impacts of Read- and Write-Assist circuits on the GeOI FinFET 6T SRAM cells compared with the SOI counterparts. The Word-Line Under-Drive (WLUD) Read-Assist is more efficient to improve the Read Static Noise Margin (RSNM) and Read VMIN of FNSP GeOI FinFET SRAM cells compared with the SOI counterparts. GeOI FinFET SRAM cells with WLUD show smaller cell Read accesstime compared with the SOI FinFET SRAM cells at both 25 degrees C and 125 degrees C. Negative Bit-Line (NBL) Write-Assist is more efficient to improve the Write Static Noise Margin (WSNM) than VCS (cell supply) lowering for both GeOI and SOI FinFET SRAM cells. NBL Write-Assist shows larger WSNM improvement for GeOI FinFET SRAM cells than the SOI counterparts at 125 degrees C.
Analysis of GeOI FinFET 6T SRAM Cells With Variation-Tolerant WLUD Read-Assist and TVC Write-Assist
(2015-06-01)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
This paper analyzes the impacts of read-assist and write-assist circuits on GeOI FinFET 6T SRAM cells considering intrinsic random variations, process corner, and temperature variation. The word-line under-drive (WLUD) read-assist is more efficient to improve the read static noise margin and read V-MIN of fast-N slow-P corner GeOI FinFET SRAM cells compared with the Silicon-On-Insulator (SOI) counterparts. GeOI FinFET SRAM cells with WLUD show less cell read access-time degradation compared with the SOI counterparts at both 25 degrees C and 125 degrees C. With transient voltage collapse (TVC) write-assist, the write-ability and variation tolerance of GeOI and SOI FinFET SRAM cells are improved. The temperature dependence of data retention time is different between the GeOI and SOI FinFET SRAM cells. The maximum TVC write-assist pulsewidth constrained by the data retention failure is smaller in GeOI FinFET SRAMs at 25 degrees C and becomes comparable at 125 degrees C compared with the SOI FinFET SRAMs.
Device Design and Analysis of Logic Circuits and SRAMs for Germanium FinFETs on SOI and Bulk Substrates
(2013)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
A comparative analysis of Germanium-on-Insulator FinFET (GeOl FinFET) and Germanium on bulk substrate FinFET (Ge bulk FinFET) at device and circuit level with respect to Si counterparts is presented. GeOI FinFET shows larger leakage current than Ge bulk FinFET due to the parasitic bipolar effect triggered by the band-to-band tunneling (BTBT) leakage. The effectiveness of different dual-Vt technology options including increasing channel doping, increasing gate length and drain-side underlap for leakage reduction is analyzed for GeOl and Ge bulk FinFET circuits and SRAMs. An optimum asymmetrie underlap design in SRAM using asymmetrie underlap pull-up and access transistors (PUAX-asym) is proposed. GeOl and Ge bulk FinFETs with asymmetrie underlap design show significant improvement in leakage-delay performance and stability in logic circuits and SRAM cells.
Threshold Voltage Design and Performance Assessment of Hetero-Channel SRAM Cells
(2013-01-01)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
Optimized threshold voltage (Vt) design to enhance the variation immunity of high-performance (super-threshold) and low-voltage (near-/sub-threshold) 6 T SRAM cells is presented. For low-voltage SRAM cells operating at low Vdd, low-Vt design shows smaller variability, while the design tradeoff between performance and leakage should be considered. For high-performance SRAM cells operating at high Vdd, ultra-thin-body SOI SRAM cells with high-Vt design show smaller variability while sacrificing performance compared with the low-Vt design. Our study indicates that hetero-channel SRAM cells enable high-Vt design and exhibit improved Read/Write stability and performance, and maintain comparable RSNM variations for the high-performance SRAM applications.
Design and Analysis of Robust Tunneling FET SRAM
(2013-03-01)
Chen, Yin-Nien
;
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Su, Pin
;
Chuang, Ching-Te
With a steep subthreshold slope, tunneling FETs (TFETs) are promising candidates for ultralow-voltage operation compared with conventional MOSFETs. However, the delayed saturation characteristic and the broad soft transition region result in a large crossover region/current in an inverter, thus degrading the hold/read static noise margin (H/RSNM) of TFET SRAM cells. The write-ability and write static noise margin (WSNM) of TFET SRAM cells are constrained by the unidirectional conduction characteristics and large crossover contention of the write access transistor and the holding transistor. In this paper, we present a detailed analysis of TFET circuit switching/output characteristics/performance and the underlying physics. The stability/performance of several TFET SRAM cells are then analyzed/compared using atomistic technology computer-aided design mixed-mode simulations. Finally, a robust 7T driverless (DL) TFET SRAM cell is proposed. The proposed 7T DL TFET SRAM cell, with better output characteristics in single-gate mode, and decoupled read current path from cell storage node and push-pull write action with asymmetrical raised-cell-virtual-ground write-assist, provides a significant improvement in hold, read, and write stability and performance.
Variation Tolerant CLSAs for Nanoscale Bulk-CMOS and FinFET SRAM
(2012)
Tsai, Ming-Fu
;
Tsai, Jen-Huan
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
In this paper, we propose three Current-Latch-based Sense Amplifiers (CLSA) configurations for nanoscale Bulk-CMOS SRAM and several CLSAs using FinFET devices with independently-controlled-gate. Extensive simulations suggest the proposed structures are robust against random offset errors. The proposed CLSA structures feature significant offset suppression capabilities with sigma(offset) reduction up to 74% (76%) in 40nm Bulk-CMOS (25nm FinFET-SOI) technology compared with the conventional CLSA. Meanwhile, up to 27% (52%) shorter sensing delay, 71% (77%) shorter Time-To-Sense and 73% (76%) lower bit-line power consumption are achieved in 40nm Bulk-CMOS (25nm FinFET-SOI). Finally, the proposed CLSA structures significantly enhance the sensing yield and affordable number of cells per bit-line, thus improving the array efficiency hence overall area and performance/power as well.
A Comprehensive Comparative Analysis of FinFET and Trigate Device, SRAM and Logic Circuits
(2012)
Pao, Chia-Hao
;
Fan, Ming-Long
;
Tsai, Ming-Fu
;
Chen, Yin-Nien
;
Hu, Vita Pi-Ho
We present a comprehensive comparative analysis of FinFET and Trigate device characteristics, 6T SRAM stability and logic circuits. The impact of intrinsic random device variations, including fin Line Edge Roughness (LER), Work Function Variation (WFV) and fin width scaling on FinFET and Trigate device Subthreshold Slope (S. S.), V-T, 6T SRAM Read Static Noise Margin (RSNM) and Write Static Noise Margin (WSNM) are investigated and compared by using 3D atomistic TCAD simulation. The results indicate that Trigate device shows slightly better variability control under the same electrical width and fin width (10nm and 7nm) considering fin LER and WFV. Next, we investigate the impact of single charged trap induced Random Telegraph Noise (RTN) on FinFET and Trigate device characteristics, 6T SRAM and logic circuits. The top-gate and the lower fin height of Trigate device under the same electrical width and fin width cause the current density to concentrate close to the bottom of the fin, resulting in stronger dependence on the location of the trap, larger RTN Delta I-D/I-D amplitude and larger Delta V-T with a trap placed at the worst position under fin LER and WFV. The impact of RTN trapping/detrapping on 6T SRAM RSNM, the leakage-delay of inverter, Two-Way NAND and 2-To-1 Multiplexer (MUX) are examined. With degreasing supply voltage, the RTN degradation of Trigate SRAM RSNM and logic circuits become larger compared with the FinFET counterparts.
Impacts of Random Telegraph Noise on FinFET Devices, 6T SRAM cell, and Logic Circuits
(2012)
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Chen, Yin-Nien
;
Su, Pin
;
Chuang, Ching-Te
This paper analyzes the impacts of single trap induced Random Telegraph Noise (RTN) on scaled FiriFET devices in tied-gate and independent-gate modes, 6T SRAM cell and logic circuits. The dependence of RTN amplitude on trap location, EOT and temperature is evaluated through 3D atomistic TCAD simulations. It is observed that charged trap located near the bottom of sidewall (gate) interface, in the middle region between the source/drain results in most significant impact. EOT scaling and higher temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependency on the location of the trap and current conduction path are analyzed. We show that planar BULK device, with larger Subthreshold Swing (S.S.) and comparable trap-induced V-T shift (Delta V-T), exhibits less nominal RTN degradation than FinFET for trap placed in the worst position. However, the larger variability and surface conduction characteristic of planar BULK device result in broader dispersion and larger worst-case degradation than FinFET with smaller variability and volume conduction inside the silicon fin. For FiriFET 6T SRAM cell, the READ Static Noise Margin (RSNM) of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage (V-dd), the relative importance of RTN on the cell stability increases. The leakage/delay of FinFET inverter, 2-Way NAND and 2-To-1 multiplexer are investigated using mixed-mode TCAD simulations. The existence of RTN is found to cause similar to 24-27% and 13-15% variation in leakage and delay at V-dd=0.4V, respectively, for the logic circuits evaluated.

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